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for further information contact your local stmicroelectronics sales office. no v e mb er 2 012 doc id 0 2313 9 re v 1 1 /82 1 stm32f437xx arm cor t e x-m4 32b mcu+fpu , 210dmi ps , up to 2m b flash/256+4kb ram, cr ypto , u sb o t g hs/fs , ether net, 17 tims , 3 adcs , 20 comm. interf aces & camer a da ta b r i e f features core: arm 32-bit cortex? - m4 cpu w i th fpu, ad ap tiv e re al- t im e ac ce ler a t o r (a rt acc e lerator? ) allowing 0-wait s t ate exec ution f r o m f l ash mem o ry, fr equ en cy up t o 16 8 m hz, me mor y pr ot ect i on u n it , 2 1 0 d mi ps/ 1. 25 dmi ps/ mhz (dh r ysto ne 2. 1) , a n d dsp instruc t ions me mor i es ? u p t o 2 m b yt e of flash me mor y ? u p t o 2 56+4 k b y t e s of sram in clu d ing 64- kb yt e o f ccm (cor e cou p le d me mor y) dat a ra m ? f le xib l e static memor y controller su pp or ti ng comp act fla s h , sram, ps ram, n o r and nan d memor i es lcd p a r a lle l in te rf ace, 80 80/ 68 00 mo de s clock, re se t a nd sup p ly m ana gem ent ? 1 .8 v to 3. 6 v a p p lica t io n su pp ly a n d i/o s ? p or, pdr , pvd and bor ? 4 -to-26 mhz cr ystal osc illator ? i n t e r n a l 16 mhz f a ct or y-t r imme d rc (1 % acc u r a cy) ? 32 khz oscillator f o r r t c with c a libr a tion ? i nter nal 32 khz rc with ca libr a tion lo w p o w e r ? s leep , st op an d sta n d b y mod e s ?v ba t sup p ly f o r r t c , 203 2 bit b a c kup re giste r s + op t i ona l 4 kb ba c k u p sram 312-bit, 2.4 m sps a / d co nverters: up to 24 channels and 7.2 m sps in triple interleaved mo de 212 -b it d/ a con v e r t e r s ge ner al- p u r p o se dm a: 16 -st r e a m dma cont r o ller wit h fi fo s an d bu rst sup p o r t up t o 17 time rs: up t o t w elve 1 6 - b it an d t w o 3 2 - b i t t i me rs u p to 16 8 m hz, e a ch w i th u p t o 4 i c / o c/ pwm o r pu lse co unt er and qua dr at ur e (in crem ent a l ) en co der inpu t debu g mod e ? s er ial wire deb ug (swd) & jt a g interf aces ? c o r te x- m4 emb e d ded t r ace ma cr ocell? up to 140 i/o ports with interrupt capability ? u p to 1 36 f a st i / o s up t o 84 mhz ? u p to 1 38 5 v - t oler ant i/ o s up to 2 0 co m m u n i ca tion in te rf ac es ? u p to 3 i 2 c int e r f aces ( s mbus/ p mbus) ? u p to 4 usar ts /4 u a r t s (1 0. 5 m b i t/ s , i s o 78 16 in te rf ac e , l i n, ir d a , m o de m co nt ro l ) ? u p t o 6 spis (4 2 m b i ts /s) , 2 w i th m u x e d f u ll- du ple x i 2 s t o ac hie v e au dio class accur a cy via in te r n al aud io pll o r e xt e r n al cl oc k ? 2 can interf aces (2.0b activ e ) ? s di o in te rf ac e advan c e d conn ect i vit y ? u sb 2. 0 f u ll- sp ee d de vice/ h o s t / o tg co nt ro ller wit h on -chip phy ? u sb 2. 0 h i gh- spee d/ fu ll-spe e d d e v i ce /h ost / o t g co nt ro ller wit h de dic a t e d dma, on -chip f u ll-spe ed phy a nd ulpi ? 1 0 / 1 00 et he r n et ma c wit h d ed i ca te d dma: s u p p o r ts iee e 1 5 8 8 v 2 ha rd w a r e , mi i/r mi i 8 - t o 14 -b it pa ra llel ca me r a in te rf ac e up to 54 m b yt es/ s crypt o g r a phi c acceler a t i on : h a r d war e acceleration for aes 128, 192, 256, triple des, hash (md5, sh a-1, s h a-2), and hmac tr ue r an dom n u mb er g ene ra to r crc calculat io n unit 96 -b it un iqu e id rt c: su bs ec on d ac cu ra cy, ha r d wa r e c a le n d a r t a b le 1. de vice su mm ar y re f e r e nc e p a r t n u mber stm32 f 43 7xx stm32f437v g, st m3 2f437zg, STM32F437IG, stm32f437 vi, stm32f437zi, stm32 f 4 37ii lqfp 100 (14 14 mm) lqfp144 (20 20 mm) fbga ufbga176 (10 10 mm) lqfp176 (24 24 mm) www.st.com http://
contents stm32f437xx 2/82 doc id 023139 rev 1 contents 1 i ntr oduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 d esc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. 1 f ull compatibility through out the f a mily . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 functional o ver vie w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. 1 a rm ? cor t e x ?-m4f core with embedde d fla s h a nd sram . . . . . . . . . 14 3. 2 a daptiv e real-time memor y acceler a tor (ar t acceler a to r?) . . . . . . . . . 14 3. 3 m emor y prot ection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. 4 e mbed ded flash memor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. 5 c rc (cyclic redun dancy ch ec k) calculation unit . . . . . . . . . . . . . . . . . . . 15 3. 6 e mbed ded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. 7 m ulti-ahb b u s matr ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. 8 m ulti-ahb matr ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. 9 d ma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. 10 fle x ib le static memor y controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 17 3. 11 ne sted v ecto r ed in terr up t con t roller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 17 3. 12 exter nal interr upt/e v ent controller (exti ) . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. 13 cloc ks and star tup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. 14 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. 15 p o w e r supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. 16 p o w e r supp ly super visor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. 17 v o ltage re gula t or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. 18 re al-time cloc k (r tc), b a c k u p sram and bac kup register s . . . . . . . . . . 22 3. 19 lo w-po w e r modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3. 20 v ba t oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3. 21 timers and w a tchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 . 2 1 . 1 a d v a n ce d - co n t ro l t i me rs ( t i m 1 , ti m 8 ) . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 3 .2 1 .2 g en er a l -p u r p o s e tim e r s ( t im x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 3 . 2 1 . 3 b a sic tim e r s tim 6 a n d tim 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 3 . 2 1 . 4 i n d e p e n d e n t w a tc hd og . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 3 . 2 1 . 5 w in d o w w a tch d o g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6
stm32f437xx contents doc id 023139 rev 1 3/82 3 .2 1 .6 s ys tic k tim e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 3. 22 inter-integ r a ted circuit interf ace (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3. 23 un iv ersal synchrono us/a syn chron ous receiv er tr ansmitters (usar t ) . . . 27 3. 24 ser i al per ipher a l interf ace (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3. 25 inter-integ r a ted sou nd (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3. 26 a udio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3. 27 secure digital input/ output interf ace (sdio) . . . . . . . . . . . . . . . . . . . . . . . 29 3. 28 ether n e t ma c inte rf ace with dedicated dma and ieee 158 8 su ppor t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3. 29 controller area netw o r k (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3. 30 un iv ersal ser i al b u s on-the - go full-speed (o tg_fs) . . . . . . . . . . . . . . . . 30 3. 31 un iv ersal ser i al b u s on-the - go high-speed (o tg_hs) . . . . . . . . . . . . . . . 30 3. 32 digital camer a interf ace (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3. 33 cr yp tog r aphic acceler a tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3. 34 ra ndom n u mb er gen er ator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3. 35 gener a l-pur pose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 32 3. 36 analog-to-digital con v er ters (adcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3. 37 t e mper ature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3. 38 digital-to-analog con v er ter ( d a c ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3. 39 ser i al wire jt a g deb ug por t (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3. 40 embed ded t r ace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 p inouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5 m emor y mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6 p ac ka g e c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6. 1 p ac kage mech anical d a ta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6. 2 t her mal char acter i stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7 p ar t n u mbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 appendix a a pplication b l oc k dia g rams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 a.1 m ain app lications v e rsus pac kage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 a.2 a pplication e x ample with regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . 72
contents stm32f437xx 4/82 doc id 023139 rev 1 a.3 u sb o t g full sp eed (fs ) interf ace solutio n s . . . . . . . . . . . . . . . . . . . . . . 73 a.4 u sb o t g hig h sp eed (hs) in terf a c e solu tions . . . . . . . . . . . . . . . . . . . . . 75 a.5 c omplete audio pla y er solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 a.6 e ther net interf ace solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
stm32f437xx list of tables doc id 023139 rev 1 5/82 list of tab l es tab l e 1. de vice su m m a r y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 tab l e 2. stm3 2 f 4 3 7 x x fe a t u r e s a n d pe rip h e r al c o u n t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 tab l e 3. time r fe at ur e com p ar iso n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 tab l e 4. co mp a r iso n o f i2 c an a l og a n d d i git a l filte r s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 tab l e 5. usar t fe atu r e c o m p ar iso n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 tab l e 6. le g e n d / a b b r e via tio n s us ed in th e p i no ut ta b l e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 tab l e 7. stm3 2 f 4 3 x p i n an d b a ll d e f in itio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 tab l e 8. fsmc p i n de fin i tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 tab l e 9. alte rn at e fu nc tion m a pp in g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 tab l e 10 . s tm3 2 f 4 3 x r e g i st er b o u n d a r y ad d r e sse s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 t a b l e 11 . l q p f 1 0 0 ? 1 4 x 1 4 mm 10 0- pin lo w- pr of ile qu ad f l at p a ck ag e m e c h a n ic al da ta . . . . . . . . 6 2 ta ble 1 2 . l qfp1 44, 20 x 2 0 mm, 14 4-p i n low- pr of ile qua d f l at p a ckage m e chan ical dat a . . . . . . . . 64 t a b l e 13 . u f b g a 17 6+ 25 - u l tra t h in f i ne p i tch b a ll gr id ar ra y 10 10 0. 6 mm m e ch a n ic al d a t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 ta ble 1 4 . l qfp1 76, 24 x 2 4 mm, 17 6-p i n low- pr of ile qua d f l at p a ckage m e chan ical dat a . . . . . . . . 67 tab l e 15 . p ac ka ge t h e r m a l ch ar a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 tab l e 16 . or d e r ing in fo rm at ion s ch e m e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 0 tab l e 17 . m ain a p p lica t io ns ve rs us pa ck ag e fo r stm 3 2f4 3 7 xx m i cro co n t ro lle rs . . . . . . . . . . . . . . . 7 1 tab l e 18 . f ull d o cu m e n t r e v i sion h i st or y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1
list of figures stm32f437xx 6/82 doc id 023139 rev 1 list of figures fig u r e 1. com pat ible boa rd d e sign stm 32f 10xx/st m32 f 2xx/stm 32f 4 x x fo r l q fp 10 0 pa ck ag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 fig u r e 2. com pat ible boa rd d e sign b e t w e e n stm 32f 10xx/st m32 f 2xx/st m 32f 4xx fo r l q fp 14 4 pa ck ag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 fig u r e 3. com pat ible boa rd d e sign b e t w e e n stm 32f 2xx an d stm3 2f4xx fo r lq fp1 7 6 p a c k a g e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 figu re 4 . stm3 2 f 4 3 x b l oc k d i a g r a m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figu re 5 . re gu lat o r o n /in t e r n a l re se t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 fig u r e 6. st ar tu p in re gu lat o r o ff: slo w v dd slop e - po we r- do wn r e se t rise n a fte r v cap_1 /v ca p _ 2 stabiliz ation . . . . . . . . . . . . . . . . . . . . . . . . 22 fig u r e 7. st ar tu p in re gu lat o r o ff mod e : fa st v dd slope - po we r- do wn r e se t rise n b e f o r e v cap_1 /v cap_2 s t abiliz ation . . . . . . . . . . . . . . . . . . . . . . 22 figu re 8 . stm3 2 f 4 3 x l q fp1 0 0 pin o u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figu re 9 . stm3 2 f 4 3 x l q fp1 4 4 pin o u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figu re 1 0 . s tm3 2 f 4 3 x l q fp1 7 6 pin o u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figu re 1 1 . s tm3 2 f 4 3 x u f bg a1 76 b a llou t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 figu re 1 2 . m em o r y ma p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 figu re 1 3 . l q f p10 0 , 1 4 x 14 m m 1 0 0 - p i n low - p r o f ile q u a d fla t p a cka ge o u t line . . . . . . . . . . . . . . . . 6 2 figu re 1 4 . r e co m m e nd e d f o o t p r in t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 figu re 1 5 . l q f p14 4 , 2 0 x 20 m m , 1 4 4 - pin lo w-p r o f ile q u a d fla t pa cka g e ou tlin e . . . . . . . . . . . . . . . . 6 4 figu re 1 6 . r e co m m e nd e d f o o t p r in t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 f i gu re 1 7 . u f b g a 17 6+ 25 - u l tra t h in f i ne p i tch b a ll gr id ar ra y 10 10 0. 6 mm , pa ck ag e ou tlin e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 fig u r e 18 . l qfp1 76 24 x 24 mm , 17 6-pin lo w- pr of ile qu ad f l at packag e out lin e . . . . . . . . . . . . . . . . 67 figu re 1 9 . l q f p17 6 r e co m m en de d fo o t pr in t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 figu re 2 0 . r e g u l at or o f f/ int e r n a l r e s e t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 figu re 2 1 . r e g u l at or o f f/ int e r n a l r e s e t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 fig u r e 22 . u sb co nt ro ller con f ig ur ed as pe rip her al- o n l y an d used in fu ll s p e e d m o de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 fig u r e 23 . u sb co nt ro ller con f ig ur ed as ho st - only and used in f u ll spee d mo de. . . . . . . . . . . . . . . . . 73 figu re 2 4 . u sb con t r o lle r co nf igu r e d in du a l m o d e a n d u se d in f u ll sp ee d m o d e . . . . . . . . . . . . . . . . 7 4 fig u r e 25 . u sb co nt ro ller con f ig ur ed as pe rip her al, host , o r dua l-m ode an d u sed in h i g h s p e e d mo d e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 figu re 2 6 . c o m p l e t e au d i o pla ye r solu tio n 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 figu re 2 7 . c o m p l e t e au d i o pla ye r solu tio n 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 figu re 2 8 . a ud io p l ay er so lut i on u sin g pll , pll i 2 s , usb an d 1 cry sta l . . . . . . . . . . . . . . . . . . . . . . . 7 7 figu re 2 9 . a ud io pl l (pl l i 2s ) p r o vid in g a cc u r a t e i2 s clo ck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 figu re 3 0 . m ast e r clo c k (m ck ) u s e d to d r ive t h e e x te rn a l a u d i o dac . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 figu re 3 1 . m ast e r clo ck (m ck ) n o t u se d to d r ive th e e xte rn a l au d i o dac . . . . . . . . . . . . . . . . . . . . . . 7 8 figu re 3 2 . m ii m o de u sin g a 25 m h z cr yst al . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figu re 3 3 . r m ii with a 5 0 mh z o sc i lla t o r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 figu re 3 4 . r m ii with a 2 5 mh z c r ys ta l a n d phy with pl l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0
stm32f437xx introduction doc id 023139 rev 1 7/82 1 intr oduction th is d a t abr i e f pro vide s t he de scr i p t io n of th e stm32 f 43 7xx lin e of microco n t r o llers . f o r m o r e de ta ils o n th e wh ole st m i cr oe lec t ro n i cs stm 3 2? f a m ily , p l ea se r e f e r to se ct ion 2 .1 : full c o mpatibility throughout the f a mily . th e st m32 f 43 7xx dat ash eet sho u ld be re ad in con j un ct ion with t he stm32 f 4xx r e f e r ence ma n u a l . th e re f e re nce ma n ual is a v ail a b l e fr om t h e stm i cr oe lect ron i cs w e bsit e w w w . st.c om . it in clu d e s all inf o r m at io n co ncer ning f l ash mem o r y pr og r a mmin g. f o r inf o r m a t io n on t h e cor t e x?- m4 cor e , p l ease r e f e r t o t he cor t e x?- m4 p r og r a mm ing m a n u al (pm 0 21 4) a v aila b l e fr om www . st. com .
description stm32f437xx 8/82 doc id 023139 rev 1 2 description th e stm3 2f4 3 7 xx d e vice s is base d on t h e h i gh- pe rf or man c e arm ? co r t e x ?-m 4 32- bit ri sc cor e ope r a t i ng at a f r equ ency of u p to 168 m h z. t he cor t e x -m4 cor e f e a t u r es a f l oa tin g po int u n it (f pu ) s i ng le pr ec isio n whic h su pp or ts all arm sin g l e- pr ec isio n da ta - pr oc es sin g in str u c t io ns a n d d a t a t y p e s . it a l so im ple m en ts a fu ll se t of dsp in str u c t io ns an d a me m o r y pr ot ect i on u n i t ( m pu ) whic h en ha n c e s a p p lica t io n se cu rity . t h e co rte x - m 4 c o r e with fpu will be referred to as co rtex-m4f thro ughout this document. th e stm3 2f4 37xx d e vices in cor p or a t es h i gh- spee d em bed ded m e mo r i es (fla sh m e mo r y u p to 2 m b yt e s , up t o 25 6 k b y t e s of sram) , up to 4 k b y te s o f ba c k u p sram , an d an e x t e n s i v e r ang e of enh an ce d i/ os an d per ip he r a ls co nne cte d to t w o apb b u ses , tw o ahb b u ses an d a 32- bit m u lt i-ahb b u s ma tr ix. all de vices of f e r t h r e e 1 2 - b it adcs , t w o d a cs , a lo w-p o w e r r t c , tw elv e ge ner al- pur po se 1 6 - b it t i me rs in cludin g tw o pwm t i me rs f o r mot o r co nt ro l, t w o ge ner al- pur po se 3 2 - b it t i me rs . a t r ue r and om n u mbe r ge ner a t or ( r ng ) , a n d a cr yp to g r ap hic acce ler a tio n cell. t h e y also f e a t u r e st an dar d an d adv a n ced com m u nicat i on int e r f a c e s . up to t h ree i 2 cs six s p is tw o i 2 ss f u ll d uple x . t o a c h i e v e au dio class a c cu r a cy , th e i 2 s pe r i ph er als can be cloc k e d via a d e d i ca te d int e r nal au dio pl l or via an e x te r n a l clo c k t o allo w sy nc hr on iza t io n. f o ur usar ts p l us f o ur u a r t s t w o usb o t g f u ll- sp ee d wit h in te r n a l phy or o ne usb o t g high - s pe ed ( with ulpi int e r f ace) p l us o n e usb o t g f u ll- sp eed wit h int e r n a l phy tw o c a n s an sd io/mmc interf ace th e adv anced p e r i p her als in clude an en han ce d f l e x ib le st at ic m e mo r y co nt ro l ( f smc) in te rf ace ( f o r de vices of f e r ed in pa c k age s o f 10 0 pin s an d mor e ) , a cam e r a in te rf ace f o r cmo s sen s o r s and a cr ypt o g r a phi c acceler a tion cell. r e f e r to t a b l e 2 : stm3 2f4 37xx f e a t u r e s an d pe r i phe r a l cou n t s f o r t h e l i st of p e r i p her als a v aila b l e on ea ch par t n u mb er . t h e st m 3 2f 4 3 7 xx d e vic e s ope r a t e s in t h e ? 4 0 to + 1 0 5 c t e m p er a t ur e r a ng e fr om a 1. 8 to 3 . 6 v p o w e r sup p ly . th e sup p ly v o lt ag e can dr op to 1. 7 v whe n t h e de vice o p e r at es in th e 0 t o 70 c t e m per a t ure r a n ge an d an in v e r t ed r e set sig nal is app lied t o pdr_ on. a com p re he nsiv e se t o f po w e r- sa vin g mod e allo ws t h e d e sign o f lo w-po w e r a ppli c a t io ns . th e stm3 2f4 37xx de vices o f f e rs de vice s in 3 pac kag e s r a n g ing fr om 1 00 pi ns t o 1 76 p i ns . th e set o f in clu ded p e r i p her als ch ang es wit h t he de vice cho s en. th ese f eat u r es mak e th e stm32 f43 7xx m i cr ocon tr olle r s su ita b le f o r a wide r a nge o f applications: mo to r dr iv e a nd ap plicat ion co nt ro l me dical equ ipme nt in d u s t r i al ap p licat ion s: pl c , in v e r t e r s , c i rc uit br ea k e rs pr int e r s , a n d scann er s alar m syst ems , video intercom, and h v a c home a udio app liance s
stm32f437xx description doc id 023139 rev 1 9/82 f i gur e 4 sho w s t h e g e n e r a l b l oc k dia g r a m of t he de vice f a m ily . t a b l e 2. st m32 f 4 3 7 xx f eat ure s and p e ri phe ral coun ts p er i pherals st m32f43 7 v x s tm32f 437z x s tm32f 437ix f l ash memor y in kb ytes 1024 2048 1024 2048 1024 2048 sram in kb ytes system 256(11 2+ 1 6 + 6 4 + 6 4 ) bac k up 4 fsmc memor y controller y es (1) ether net ye s ti me rs gener al-pur pose 10 a d v a nc e d - c o nt r o l 2 basi c 2 ra ndom n umber ge ner ator ye s co mm unication inter f ac es spi / i 2 s 6 /2 (fu l l duple x ) (2) i 2 c 3 usar t/u a r t 4/4 usb o t g fs y e s usb o t g hs ye s can 2 sdio ye s ca mer a int e rf ace ye s cr yp tog r a p h y ye s gpios 8 2 114 140 12-bit a d c nu mber of channels 3 1 6 24 24 12-bit d a c nu mber of channels ye s 2 maxim u m c p u freque ncy 168 mhz oper ating v o ltage 1.8 to 3 .6 v (3)
description stm32f437xx 10/82 doc id 023139 rev 1 oper ating temper a t ures ambient tempe r atures: ?40 to + 85 c /?40 to +105 c j unction t emper ature : ?40 to + 125 c p a c k a g e l qf p 1 00 lqfp144 u f bga176 lqfp176 1. for the lqfp100 p a ckage, only fsmc bank1 or bank2 are available. bank 1 can only support a multiplex ed nor/psram memory using the ne1 c h ip select. bank2 can only suppor t a 16- or 8-bit n a nd flash memo ry usin g the nce2 c hip select. the interrupt line cannot be used s inc e port g is not ava i lable in th is package . 2. the spi2 an d spi3 inte rfaces g i ve the fl exibility to work in an e xclusive wa y in either the sp i mode or th e i2s audio mode. 3. v dd /v dda minimum value o f 1.7 v is obtained w hen the device o perates in the 0 to 70 c temperature range a nd an inverted re set signal is applied t o pdr_on. t a b l e 2. st m32 f 4 3 7 xx f eat ure s and p e ri phe ral coun ts ( c on ti n u ed) p er i pherals st m32f43 7 v x s tm32f 437z x s tm32f 437ix
stm32f437xx description doc id 023139 rev 1 11/82 2. 1 full compati b ili ty t h r o ughout the fami l y th e stm3 2f4 37xx a r e p a r t o f t h e stm 32f 4 f a mily . the y are fu lly pin - t o - p in , sof t w ar e an d f e at ur e co mp a t ib le wit h the s t m 3 2f 2 xx de vice s , a llo win g th e us er to t r y dif f e r e n t m e m o r y d ensit ies , pe r i phe r a ls , an d pe rf or m ance s (fpu , h i gh er f r e que ncy) f o r a g r ea te r de g r e e of freedom dur i ng the de v e lopment cycle . the stm32f437xx de vices maintain a c l os e c o mpatibility with the w h ole stm32f10xx f a m ily . all f unct i on al pins ar e pin - t o - p in com pat ib le . the stm32 f 43 7xx, ho w e v e r , a r e n o t drop-in replacements f o r the stm32f10 xx de v i ce s : the tw o f a milies do not ha v e the same p o w e r sche m e , a nd so th eir p o w e r pins ar e dif f er ent . no net he less , t r a n sitio n f r o m t h e stm 32f 10xx t o t h e stm 32f 43x f a mily rem a ins simple a s on ly a f e w p i ns a r e im pact e d . fig u r e 1 , figu re 2 , an d figu re 3 , giv e co mpa t ib le bo ar d de sig n s b e t w e en t h e stm 32f 4xx, stm32f2xx , and s t m32f10x x f a milies . fi gu re 1. compa t i b l e boar d des i gn stm32 f 10 xx /stm 32f 2xx /stm 32f 4xx f o r l q fp10 0 pac k a g e 20 49 12 5 26 50 51 75 100 76 73 19 v ss v ss v dd v ss v ss v ss 0 resistor or soldering bridge present for the stm32f10xxx configuration, not present in the stm32f4xx configuration ai18488c 99 (v ss ) v ss v dd two 0 resistors connected to: - v ss for the stm32f10xx - v ss for the stm32f4xx v ss for stm32f10xx v dd for stm32f4xx - v ss , v dd or nc for the stm32f2xx
description stm32f437xx 12/82 doc id 023139 rev 1 figu re 2. compa t ib le boar d des i gn bet w e e n stm3 2f10 xx /st m 32 f2x x /st m 32 f4 x x f o r l q fp14 4 pac k a g e figure 3. compatible board design between stm32f2xx and stm32f4xx for lqfp176 package 31 71 13 6 37 72 73 108 144 109 v ss 0 resistor or soldering bridge present for the stm32f10xx configuration, not present in the stm32f4xx configuration 106 v ss 30 t wo 0 resistors connected to: -v ss for the stm32f10xx -v dd or inverted reset signal for the stm32f4xx v ss v dd v ss v ss ai18487c 143 (pdr_on) v ss v dd v ss for stm32f10xx v dd for stm32f4xx - v ss , v dd or nc for the stm32f2xx inverted reset signal 144 45 88 89 132 176 133 t wo 0 resistors connected to: - v ss , v dd or nc for the stm32f2xx -v dd or inverted reset signal for the stm32f4xx ms19919v2 171 (pdr_on) v ss v dd inverted reset signal
stm32f437xx description doc id 0 2313 9 re v 1 13/82 fi gu re 4. stm 32f 43x b l oc k di a g ra m 1. the timers connected to apb2 are clocked from timxclk up to 168 mhz, while the timers connected to apb1 are clocked from timxclk either up to 84 mhz or 168 mhz. gpio port a ahb/apb2 ext it . wkup 140 af pa[15:0] tim1 / pwm ompl. channels (tim1_ch1[1:4]n, 4 channels (tim1_ch1[1:4]etr, bkin as af usart1 rx, tx, ck, cts, rts as af spi1 mosi, miso, sck, nss as af apb2 60mhz apb1 30mhz 8 analog inputs common to the 3 adcs vddref_adc uar t4 mosi/sd, miso/sd_ext, sck/ck nss/ws, mck as af sp3/i2s3 tx, rx bxcan2 dac1_out af itf wwdg 4 kb bkpsram r tc_af1 osc32_in osc32_out vdda, vssa nrst smcard irda 16b sdio / mmc d[7:0] cmd, ck as af vba t = 1.65 to 3.6 v dma2 scl, sda, smba as af i2c3/smbus jt ag & sw arm cortex-m4 168 mhz nvic etm mpu traceclk traced[3:0] ethernet mac 10/100 dma/ fifo mii or rmii as af mdio as af usb otg hs dp, dm ulpi:ck, d[7:0], dir, stp, nxt id, vbus, sof dma2 8 streams fifo art accel/ cache sram 1 12 kb clk, ne [3:0], a[23:0], d[31:0], oen, wen, nbl[3:0], nl, nreg, nw ait/iordy , cd intr as af rng camera interface hsync, vsync puixclk, d[13:0] phy usb otg fs dp dm id, vbus, sof fifo ahb1 168 mhz phy fifo us art 2mbps temperature sensor adc1 adc2 adc3 if if @ vdda @vdda por/pdr bor supply supervision @vdda pvd int por reset xt al 32 khz ma n a gt rtc rc hs fclk rc ls pwr interface iwdg @v bat @vdda @v d d awu reset & clock control pll1&2 pclkx vdd = 1.8 to 3.6 v vss vcap1, vcp a2 v oltage regulator 3.3 to 1.2 v vdd power managmt @vdd r tc_af1 backup register ahb bus-matrix 8s7m apb2 84 mhz ls tim14 tim9 2 channels as af dac1 dac2 flash up to 2 mb sram, psram, nor flash, pc card (a t a), nand flash external memory controller (fsmc) tim6 tim7 tim2 tim3 tim4 tim5 tim12 d-bus ms30414v2 fifo fpu apb142 mhz (max) sram 16 kb ccm data ram 64 kb ahb3 ahb2 168 mhz njtrst , jtdi, jtck/swclk jtdo/swd, jtdo i-bus s-bus dma/ fifo dma1 8 streams fifo pb[15:0] pc[15:0] pd[15:0] pe[15:0] pf[15:0] pg[15:0] ph[15:0] pi[1 1:0] gpio por t b gpio por t c gpio por t d gpio por t e gpio por t f gpio por t g gpio por t h gpio por t i tim8 / pwm 16b 16b tim10 16b tim1 1 16b smcard irda usar t6 ompl. channels (tim1_ch1[1:4]n, 4 channels (tim1_ch1[1:4]etr, bkin as af 1 channel as af 1 channel as af rx, tx, ck, cts, r ts as af 8 analog inputs common to the adc1 & 2 8 analog inputs for adc3 dac2_out af 16b 16b bxcan1 i2c2/smbus i2c1/smbus scl, sda, smba as af scl, sda, smba as af sp2/i2s2 mosi/sd, miso/sd_ext, sck/ck nss/ws, mck as af tx, rx rx, tx as af rx, tx as af rx, tx as af cts, r ts as af rx, tx as af cts, r ts as af 1 channel as af uar t5 usar t3 usar t2 smcard irda smcard irda 16b 16b 16b 1 channel as af tim13 2 channels as af 32b 16b 16b 32b 4 channels 4 channels, etr as af 4 channels, etr as af 4 channels, etr as af dma1 ahb/apb1 ls osc_in osc_out hclkx xt al osc 4- 16mhz fifo spi4 sck, nss as af spi5 sck, nss as af mosi, miso, mosi, miso, spi6 sck, nss as af mosi, miso, rx, tx as af uart7 rx, tx as af uart8 sram 64 kb tdes, aes256 hash fifo fifo
functional overview stm32f437xx 14/82 doc id 023139 rev 1 3 functional o ver vie w 3. 1 arm ? cor t e x ?-m4f core with embed d ed fla s h and sram th e arm co r t e x -m4f p r o c e s sor is t h e la te st ge ner a t ion of arm p r o c e s so rs f o r emb edd ed syst e m s . i t w a s d e v e lo pe d to p r o v ide a lo w- co st plat f o r m th at m eet s t h e nee ds of m c u imp l em ent at ion , wit h a re duce d pin cou n t a nd lo w-p o w e r co nsump t io n, wh ile de liv e r ing o u t s t a n d in g co mpu t a t iona l p e r f o r ma nce an d an a d v a n c e d re sp on se t o int e rr up t s . th e arm co r t e x -m4f 3 2 - b it ri sc pr ocessor f e at ure s e x cep t iona l cod e - e f f i cie n cy , d e liv er in g th e hig h - per f o r m ance e x p e cte d f r om a n arm cor e in t h e me mor y siz e u s ually a s socia t e d wit h 8 - an d 16- bit de vices . th e pr ocessor sup p o r t s a se t of dsp inst r u ct i ons which allo w e f f i cien t sign al pr ocessin g a nd comp le x algo r i th m e x ecut ion . i t s sing le pr ecisio n fpu ( f loat ing p o in t un it) sp ee ds u p so f t w a re d e v e lo pme n t b y using me t a lan gua ge d e v e lo pme n t t o ols , wh ile a v o i din g sa tu r a t i on . the stm32f43x f a mily is c o mpatib le with all ar m tools and softw a re . fig u r e 4 sho w s t he g ene r a l b l oc k d i ag r a m of th e stm32 f 43 x f a m ily . no te : c o r te x- m 4 f is bin a r y c o mpatib le with c o r t e x -m3. 3. 2 adaptive real -time memor y a ccelerator (ar t accelerator?) the ar t acceler a tor? is a memor y acc e ler a to r which is o p t i miz e d f o r stm3 2 indu str y - st and ar d arm ? co r t e x ? - m 4 f pr oc es sor s . it ba lan c e s th e inh e r e nt p e r f o r m a n c e ad v a nt ag e o f t he arm co r t e x - m 4 f o v e r flash me mor y t e ch nolo g ie s , which no r m a lly r equ ire s t h e pr oc es so r t o w a it f o r t h e f l a s h m e m o r y at hig h e r fr eq u e n c ie s . to release t he p r oce s sor fu ll 2 1 0 d mi ps p e r f o r ma nce at th is f r e que ncy , th e acceler a t o r imp l em ent s a n inst r u ctio n pr ef et ch que ue a nd b r anch cache , wh ich incre a ses p r o g r a m e x e c u t i on spee d f r om t h e 128 -b it fla s h m e mo r y . based o n core mar k be nchma r k, t he p e r f o r ma nce achie v e d t han ks t o th e ar t a c cele r a t o r is e quiv a lent to 0 w a it st at e pr og r a m e x e c u t i on f r o m f l ash mem o r y at a cpu f r e que ncy u p to 1 68 mhz. 3. 3 memor y pr otection unit th e me mor y pr ot ect i on u n it ( m pu) is u sed t o man a g e th e cpu accesse s t o me mor y t o p r e v e n t one t a sk to a c cid ent ally co rr u p t th e mem o r y or r e sou r ces used b y an y o t h e r a c t i v e t a sk. th is mem o r y ar ea is o r g aniz ed int o up t o 8 pr ot ecte d ar eas th at can in t u r n be divide d u p int o 8 suba re as . the p r o t e c t i on are a siz e s ar e bet w e en 3 2 b yt e s and t h e wh ole 4 g i gab yt es o f ad dr essab l e mem o r y . the mpu is es pecially helpful f o r applic ations where s o me c r itic al o r ce r t if ied co de ha s t o be pr ot ec te d ag ain st th e m i sbe h a vio r of ot he r ta sks . it is u su a lly m a n a g e d b y an r t os (r ea l- t i me o per at ing syst e m ) . i f a pr og r a m a cce sses a me mor y loca tio n th at is pr oh ibit ed b y t h e m p u , th e r t o s ca n d e t e ct it an d ta k e ac tion . in a n r t os e n vir o n m en t, th e k e r n e l c a n d y n a mically up dat e t h e m p u ar ea set t i ng, ba se d on t h e p r o c e s s t o be e x e c u t e d . th e mpu is op tio nal a nd can b e b ypa sse d f o r ap plicat ion s t h a t do n o t nee d it.
stm32f437xx functional overview doc id 023139 rev 1 15/82 3. 4 embed d ed flash memor y th e de vice s em bed a flash me mor y o f 1 mb yte s o r 2 mb yte s a v aila b l e f o r st o r ing pr og r a ms a nd da t a. 3.5 crc (c yc lic redundanc y c h ec k) calculation unit th e crc ( c yclic r e d und ancy ch ec k) calcula t ion u n it is used to get a crc code fr om a 3 2 - b it d a t a w o rd a nd a f i x e d ge ner at or p o lyno mial. am on g ot he r ap p licat ion s , c rc- ba se d te ch niq u e s ar e us ed to v e r i fy d a t a t r an sm issio n o r st or a ge int e g r ity . i n th e sco p e o f t he en/i ec 6 0 3 35- 1 sta nda rd , t h e y o f f e r a mea n s of v e r i fying t h e flash me mor y in te g r ity . th e crc ca lcu l at ion u n it help s comp ut e a sof t w ar e sign at ur e du r i ng r u n t ime , t o be com par ed wit h a re f e re nce signa tu re g e n e r a te d at li nk-t ime a nd sto r e d at a giv e n m e mo r y locat i on . 3. 6 embed d ed sram all de vices e m b ed: up to 256 k b ytes of syst em sram including 64 kb yt es of cc m (core c o upled memor y) da ta ram ram memor y is accessed (read/wr ite) at cp u cloc k speed with 0 w a it states . 4 kb yt es of bac kup sram thi s ar ea is acce ssib le on ly f r om t he cp u . i t s con t e n t is pr ot ect ed ag ain s t possib l e un w a n t e d wr ite a c cesses , an d is r e t a in ed in st and b y or v ba t mo de .
functional overview stm32f437xx 16/82 doc id 023139 rev 1 3. 7 mul t i-ahb b u s matrix the 3 2 - b it m u lti-a h b b u s m a tr ix in te rco n n e c ts a ll th e m a st er s ( c pu , dm as , eth e r n e t, usb hs) a nd t h e sla v es ( f lash me mor y , ram, f s mc , ahb and apb p e r i ph er a l s) an d en su re s a sea m less a n d e f f i cien t op er a t io n e v en wh en se v e r a l high -spe ed p e r i ph er a l s w o r k sim u lt an eou sly . 3. 8 mul t i-ahb matrix 3. 9 dma contr o ller (dma) th e de vices f eat ur e t w o gene r a l- pu r p o se dua l-p o r t dmas ( d ma1 an d dma2) wit h 8 st re ams each. the y a r e a b le to m ana ge me mor y-t o- mem o r y , p e r i p her al-t o - me mor y a nd memor y-to-per i pher a l tr ansf ers . the y f e ature dedicate d fifos f o r apb/ahb per ipher a ls , sup por t b u rst t r a n sf e r an d ar e de sig n e d to p r o vide t h e m a xim u m pe r i ph er a l b and wi dt h (ah b /apb). th e t w o dma co nt ro ller s supp or t cir c u l ar b u ff er man age men t , so th at n o specif ic cod e is n eed ed whe n th e cont r o ller re aches th e en d of th e b u ff e r . the t w o dm a con t r o lle rs also h a v e a d oub le b u f f er in g f e at ur e , which au to mat e s th e use an d s w it chin g of t w o memo r y b u f f er s with o u t r equ ir ing a n y special cod e . ea ch st re am is con n e c t e d t o d edicat e d har dw a r e dma r equ ests , with su ppo r t f o r sof t w ar e t r igg e r o n ea ch st re am. co nf igu r at ion is mad e b y sof t w a r e and t r a n sf e r siz e s be tw een sou r ce an d de st ina t io n ar e ind epe nd ent . arm cortex-m4 gp dma1 gp dma2 mac ethernet usb otg hs bus matrix-s s0 s1 s2 s3 s4 s5 s6 s7 icode dcode accel flash memory sram 1 12 kbyte sram 16 kbyte ahb2 peripherals ahb2 fsmc static memctl m0 m1 m2 m4 m5 m6 m7 i-bus d-bus s-bus dma_pi dma_mem1 dma_mem2 dma_p2 ethernet_m usb_hs_m ms30410v2 ccm data ram 64-kbyte apb1 apb2 sram 64 kbyte m3 peripherals
stm32f437xx functional overview doc id 023139 rev 1 17/82 th e dma ca n be use d wit h t h e ma in pe r i ph er al s: spi an d i 2 s i 2 c usa r t g e n e r a l -p u r p o s e , b a sic an d ad v a nc ed -c on tr ol tim e r s t i m x da c sdio cr yptog r aphic acceler a tion camer a interf ace (dcmi) adc . 3.10 fle x ib le static memor y contr o ller (fsmc) all d e v i ce s e m be d an f s m c . it ha s f o ur ch ip sele ct o u t p u t s su pp or ting t h e f o llo w i ng m o d e s : pc ca rd /co m pa ct f l ash , sram , psram , nor f l as h an d nand f l as h. fu nct i ona lit y o v er vie w : wr it e fi fo m a xim u m f s mc_clk fr eq uen cy f o r synchr ono us a cce sses is 6 0 mhz. lcd parallel interface th e fsmc ca n be con f ig ur ed t o int e r f ace seam lessly wit h mo st g r a phic lcd con t r o lle rs . i t sup por t s t h e in te l 8 0 8 0 and m o t o r o la 6 800 m ode s , a nd is fle x ib le e nou gh t o ad apt t o spec ific lcd interf aces . this lcd par a llel interf ace c a pability mak e s i t eas y to b u ild c o st- e f f e ct iv e g r ap hic app lica t i ons using l c d mod u le s with e m be dd ed con t r o lle rs o r hig h p e r f o r ma nce so lut i on s usin g e xte r n al co nt ro ller s with ded ica t ed accele r a t i on . 3. 11 nested vectored interrupt contr o ller (nvic) th e de vice s em bed a nest ed v e ct or ed in te rr u p t con t rolle r ab le t o ma nag e 16 p r ior i t y le v e ls , a nd hand le up to 8 7 ma skab le in t e rr u p t ch an nels plu s t he 16 in te rr u p t lin es of th e cor t e x?- m4 f . closely co uple d nvi c giv e s lo w- lat e n c y int e r r up t pr ocessing i n t e r r upt ent r y v e ct or t a b l e a ddr ess p a ssed dir e ct ly t o t he cor e allo ws ea r l y pr ocessing o f int e rr up t s pr oc es sing o f late a r r i v i ng , hig h e r -p r i or ity in te rr u p t s sup por t ta il cha i nin g pr oc es sor st at e au to m a t i cally sa v e d i n t e r r upt ent r y r e sto r e d on in te rr u p t e x i t with n o inst r u ctio n o v er hea d t h is ha rd w a r e b l oc k pr o vid es fle xib le int e r r up t m a na g e m e nt f e at ur es with m i nim u m int e r r up t latency .
functional overview stm32f437xx 18/82 doc id 023139 rev 1 3. 12 external interrupt/ e v ent contr o ll er (exti) th e e x t e r n al int e r r up t/ e v e n t co nt ro ller con s ist s o f 23 e d g e -d et ect o r lin es u s ed t o ge ner a t e in te rr u p t / e v ent re que sts . each line can be ind e p end ent ly co nf igur ed t o sele ct th e t r igge r e v e n t (r isin g ed ge , f a lling e d g e , b o t h ) a n d ca n be mask ed ind epe nde nt ly . a pe ndin g r egist er m a in ta ins th e sta t u s o f th e inte r r up t r e qu es ts . th e exti c a n d e t e c t a n e x te r n a l line w i th a pulse width shor ter than the inter n al apb2 cloc k per i od. up to 140 gp ios can be connected to th e 16 e x t e r n al in te rr u p t lin es . 3. 13 cloc ks and star tup on res e t the 16 mhz inter n al rc osc illator is selected as the def ault cpu cloc k. the 16 mhz inter n al rc osc illator is f a c t or y-tr im med to off e r 1% accur a c y at 25 c . the application can then sele ct as sy stem cloc k either the r c os cillator or an e x ter n al 4-26 mhz cloc k so ur ce . this clo c k can b e mo nit o r ed f o r f a ilu re . if a f a ilur e is d e t e cte d , th e syst em automatical l y s w itches bac k to the inter n al rc osc illator and a s o ftw a re interr upt is ge n e r a te d (if en ab led ) . t h is clo c k s o u r c e is in p u t to a pl l th us allo w i ng t o in cr ea se t h e fr eq ue n cy up to 1 6 8 m h z. s i mila r l y , fu ll in te rr u p t m a n a g e m en t of th e pll c l oc k en tr y is a v ailab l e when nec e ss ar y (f or e x ample if an indirectly used e x te r n al osc illator f a ils). se v e r a l pr escale rs allo w t h e con f ig ur a t ion of th e t w o ahb b u ses , the h i gh- spee d apb (apb 2) and the lo w-speed apb (apb1) domains . the maxim u m frequency of the tw o ahb b u ses is 168 m hz w h ile t h e maxim u m frequenc y of the high-speed apb domains is 84 mhz. th e ma xim u m a llo w e d fr eq uen cy of th e lo w- spee d apb d o ma in is 42 m h z. t h e d e v i ce s e m be d a de dic a t e d pl l (pl l i 2 s ) whic h allo w s to a ch i e v e au dio c l as s pe rf or m a n ce . in t h is ca se , th e i 2 s mast er cloc k ca n ge ner at e all sta nda rd sam p ling fr eq ue n cie s fr o m 8 khz to 1 9 2 k h z. 3. 14 boot modes at st ar t u p , bo ot p i ns are u sed t o select o n e o u t o f t h r ee b oot opt io ns: bo ot fr om use r f l as h boot from syst em memor y boo t f r o m e m be dd ed sram th e bo ot lo ad er is locat e d in syst e m m e mo r y . i t is u sed t o re pr og r a m th e flash me mor y b y using u sar t1 (p a9/p a10), usar t3 (pc10/pc 11 o r pb1 0 / pb11) , can2 ( p b5 / p b1 3), usb o t g fs in de vice mo de (p a1 1/ p a 12) th ro ugh dfu (d e vice fir m w a re u p g r a de) . 3. 15 p o wer suppl y sc hemes v dd = 1.8 t o 3. 6 v : e xt e r n al po we r s u p p ly f o r i/o s an d th e int e r n a l r e g u l at or (w he n e n a b le d) , pr o vid ed e xte r n a lly t h r o ug h v dd pin s . v ssa , v dd a = 1 . 8 to 3. 6 v : e x t e r n a l ana log p o w e r supp lies f o r adc , d a c , reset b l oc ks , rcs an d pl l. v dd a a nd v ssa m u st b e co nn ecte d t o v dd an d v ss , respect i v e ly . v ba t = 1. 65 to 3.6 v : po w e r supply f o r r t c , e xter n al cloc k 32 k h z os cillator and bac kup re gist er s (t h r ou gh p o w e r s wit ch ) when v dd is n o t pr es en t.
stm32f437xx functional overview doc id 023139 rev 1 19/82 note: v dd /v dd a min i m u m v a lue of 1 . 7 v is o b t a in ed whe n th e de vice op er a t es in t h e 0 to 7 0 c t e m per at ure r a n ge an d an in v e r t ed r e set sig nal is app lied t o pdr_ on. 3. 16 p o wer suppl y super v isor th e po w e r sup p ly su per viso r is e nab le d b y hold i ng pdr_on hig h . th e de vice h a s a n int e g r a t ed po w e r - on rese t (po r ) / p o w e r - d o wn rese t (pdr) circuit r y co up le d w i th a bro w no u t r e s e t (b or) cir cu i tr y . at p o w e r - on, bor is alw a ys act i v e , an d e n sur e s pr ope r o p e r at ion st ar t i ng f r om 1. 8 v . af t e r th e 1 . 8 v bo r t h r e sho l d le v e l is re ache d, t h e o p t i on b y te l oad ing pr ocess st ar t s , eit her to con f ir m or m odif y def au lt t h r e sho l ds , or t o d i sa b l e bo r p e r m ane nt ly . thr ee bor t h re shold s ar e a v ailab l e t h r o u gh op t i on b y t e s . th e de vice r e ma ins i n rese t mo de whe n v dd is belo w a spec i f ied thres h old, v por/pdr or v bo r , wit h out th e ne ed f o r a n e xt e r n al re se t circui t. th e de vice also f e at ur es a n e m be dd ed pr og r a mma b le v o lt ag e det e c t o r ( pvd) t h a t mo nit o r s th e v dd /v dd a po w e r sup p ly and co mpa r es it t o t he v pvd t h r e s h o l d. an in te rr u p t ca n be g ene r a t e d wh en v dd /v dd a dr ops be lo w t h e v pvd t h r e s h o l d an d/ or wh en v dd /v dd a is high er th an t h e v pvd t h resh old. the in te rr u p t se r vice ro ut ine can t h e n ge ner at e a w a r n ing me ssa ge an d/ or put th e mcu in to a sa f e st at e . th e pvd is e nab le d b y so f t w a re . all pa c k ag es , e xce pt f o r th e l q f p 10 0, h a v e a n int e r n a l r e s e t c o nt ro lled thr o u g h th e pdr_on s i gnal. 3. 17 v o lta g e regulator th e re gu lat o r h a s e i gh t op er a t in g mod e s: regu lat o r o n /in t e r na l res e t on ? m a i n re gu la to r m o de ( m r ) ? l o w po w e r re gu lat o r ( l pr ) ? p ow e r - d ow n regu lat o r o n /in t e r na l res e t of f ? m a i n re gu la to r m o de ( m r ) ? l o w po w e r re gu lat o r ( l pr ) ? p ow e r - d ow n re g u la to r off/in te r n al re se t o n re g u la to r off/in te r n al re se t o f f
functional overview stm32f437xx 20/82 doc id 023139 rev 1 regul ator on regu lat o r o n /in t e r na l res e t on on l q fp1 00 pa c k age , th e re gula t or o n / i nt er na l r e set on m ode i s alw a ys en ab led . on lqfp1 44 pa c k age , th is mo de is activ a te d b y set t in g pdr_ on t o v dd . on ufbg a1 76 a nd l q fp17 6 p a c ka ges , t h e in te r n a l reg u la to r m u st b e act i v a te d b y conn ect i ng byp ass_ reg t o v ss a n d b y se tt ing pd r_o n to v dd . th er e ar e thr e e lo w-p o wer m o d e s : ? m r is used in t h e n o min a l re gu lat i on mo de ( r u n ) ? l pr is used in t h e st op m ode s ? p o w er -d o w n is used i n st a ndb y m ode : t h e r e g u lat o r out p u t is in hig h impe dan ce : th e k e r nel circuit r y is po w e red do wn, in du cin g z e r o consu m pt ion ( b ut t h e co nt en ts o f th e re gis t er s an d sram a r e lo st) . regu lat o r o n /in t e r na l res e t of f on t h e lqf p 1 0 0 p a c k age , th is mo de is not a v a ilab l e . o n lqfp1 4 4 pa c k age , t h e int e r n a l r e set is cont r o lle d by a ppl yin g an in ve rt ed r e set signal to p dr_on pin. o n uf bga 1 7 6 an d lq f p 1 7 6 p a c k ag es , th e int e r n al r e gu lat o r is ac tiv a te d b y conn ect i ng byp ass_ reg t o v ss . th e int e r nal r e set is cont r o lled b y a pplyin g an in ve rte d re se t sign a l to pd r_ on pin . v dd /v dd a minim u m v a lue o f 1. 7 v is ob t a ine d when t h e d e vice op er at e s in t he 0 t o 70 c t e mp er a t u r e r ang e an d an in v e r t ed r e set sig nal is a p p lied t o pdr_ on. th e n r st p i n sh ou ld be c o n t r o lle d b y an e x te r n a l r e s e t co nt ro ller to k e e p t h e d e vice un der re se t whe n v dd is belo w 1.8 v (s ee fig u re 5 ). figure 5. regulator on/internal reset off v dd time ms19009v5 pdr=1.7 v time nrst pdr_on pdr_on next reset asserted
stm32f437xx functional overview doc id 023139 rev 1 21/82 regul ator off th is mo de a llo ws to po w e r th e de vice a s soon a s v dd re ac he s 1 . 8 v . re g u la to r off/in te r n al re se t o n thi s mo de is a v a ilab l e on ly on ufbg a176 a nd l q fp17 6 p a c kag e s. i t is act i va te d by setting bypa ss_r e g and pdr _ on pins to v dd . th e r e gu lat o r o f f/ inte r n a l r e se t on m o d e allo ws to su p p ly ex te rn ally a 1 . 2 v vo lta g e sour ce th ro ugh v cap_1 a nd v cap_2 pins, i n add itio n t o v dd . t h e f o llo w i ng c o n d it ion s m u s t b e re sp ec te d: ?v dd sh ou ld alw a ys be h i ghe r t han v cap_1 an d v ca p _ 2 t o a v oid cur r e n t in ject ion bet w e en p o w e r d o ma ins . ? i f th e t i me f o r v cap_1 an d v cap_2 t o r each 1. 08 v is f a st er t han t he t i me f o r v dd to rea ch 1. 8 v , t hen p a 0 sho u ld b e co nne cte d to t h e nrst pin ( see fig u r e 6 ). ot her wise , p a 0 sh ould b e asser t ed lo w e x t e r n a lly du r i ng po r un t il v dd re ac he s 1. 8 v ( see fig u re 7 ). ?i f v ca p _ 1 an d v cap_2 g o belo w 1. 08 v an d v dd is h i ghe r t han 1. 7 v , th en a r e set m u st be a s se r t ed on p a 0 pin . i n re gula t o r off/ int e r n al re se t o n mo de , p a 0 can not be u s e d as a gpi o pin since it allo ws t o r e set th e pa r t o f t he 1 . 2 v log i c wh ich is no t r e set b y t he nrst pin, when t h e int e r nal v o lt a ge r egu lat o r in o f f . re g u la to r off/in te r n al re se t o f f thi s mo de is a v a ilab l e on ly on ufbg a176 a nd l q fp17 6 pa ckag es. i t is act i va te d by setting byp ass_reg pin to v dd an d by app lyin g an inve rt ed r e set sig nal t o pdr_o n . i t a llo ws t o su pp ly e xt e r n ally a 1 . 2 v v o lt ag e so ur ce t h r o u gh v cap_1 an d v cap_2 pin s , in ad dit i on t o v dd . t h e f o llo w i ng c o n d it ion s m u s t b e re sp ec te d: ?v dd sh ou ld alw a ys be h i ghe r t han v cap_1 an d v ca p _ 2 t o a v oid cur r e n t in ject ion bet w e en p o w e r d o ma ins . ? p a0 sh ou ld be k e pt lo w to co v e r b o th c o n d i tion s: u n til v cap_1 and v cap_2 r each 1. 08 v and u n t il v dd r eache s 1 . 8 v (se e figu re 6 ). ? n rst shou ld be con t r o lle d b y an e x t e r n a l r e set co nt ro ller t o k e ep t he d e vice und er r e set wh en v dd is belo w 1.8 v (see fi gur e 7 ).
functional overview stm32f437xx 22/82 doc id 023139 rev 1 figu re 6. st ar t up in re gulat or of f: slo w v dd sl op e - po we r - do wn re se t ris e n a f t e r v cap_1 /v cap_2 st abi l i zat i on 1. th is fig u re is valid b o th whatever the int ernal reset mode (on or off). figu re 7. st ar t up in re gulat or of f mo de: f a s t v dd sl op e - po wer - d o wn res e t rise n bef o r e v ca p _ 1 /v c a p_2 s t a b i liz at ion 1. th is fig u re is valid b o th whatever the int ernal reset mode (on or off). 3. 18 real-ti me c l oc k (r tc), bac k up sram a n d ba c k up re gister s th e ba c k u p do main in clu d e s : t h e r e al- tim e cloc k ( r t c ) 4 kb yt es of bac kup sram 20 b a c kup r e g i st er s th e rea l -t ime cloc k ( r tc) is an inde pe nde nt bcd t i mer / co unt er . ded i ca t ed re giste r s con t ain t h e se cond , m i n u t e , h our ( i n 12 /2 4 h our ), w eek da y , da te , mo nt h, y e a r , in bcd (b ina r y-co ded d e cimal) f o r m a t . co rr ect i on f o r 2 8 , 29 ( l eap y e ar ), 30, an d 31 da y o f t he mo nt h ar e p e r f o r me d aut om at ically . the r t c pr o vid es a p r o g r a m m ab le ala r m an d pr og r a mma b l e v dd time 1.08 v ai18491c pdr=1.7 v v cap_1 /v cap_2 1.2 v pa0 tied to nrst nrst time v dd time 1.08 v ai18492c pdr=1.7 v v cap_1 /v cap_2 1.2 v pa0 asserted externally nrst time
stm32f437xx functional overview doc id 023139 rev 1 23/82 p e r i od ic in te rr u p t s wit h w a k e up f r o m sto p and st an db y m ode s . th e sub- secon d s v a lue is a l so a v aila b l e in bina r y f o r m a t . it is c l oc k e d b y a 32.768 kh z e xter n al c r ys tal, res o nator or osc illator , the inter n al lo w-po w e r rc os cillator or the high -speed e x ter n al cloc k divided b y 128. the inter n al lo w-s p eed rc h a s a t ypical f r e que ncy o f 32 khz. th e r t c can b e ca libr a te d using a n e xt e r n al 51 2 hz o u t put t o co mpe n sat e f o r a n y na tu r a l qu ar t z de viat ion. t w o ala r m r egist er s ar e used to g ene r a t e a n alar m at a sp ecific t i me an d ca len dar fie l ds ca n b e inde pe nde nt ly ma sk ed f o r a l ar m co mpa r iso n . t o gen er a t e a per io dic int e r r upt , a 16- bit p r o g r a mm ab le bin a r y au to -r elo ad do wncou n t e r wit h pr og r a mma b l e re so lut i on is a v a ilab l e a nd allo ws a u t o m a t i c w a k eup and p e r i o d ic a l ar m s f r o m e v er y 1 20 s t o e v er y 3 6 hou rs . a 20 -bi t pr escaler is used f o r t he t i me ba se clo c k. it is b y d e f a u l t conf ig ure d t o gen er a t e a t i me b a se of 1 se co nd f r o m a cloc k a t 3 2 . 768 khz. the 4-kb yte bac kup sr am is an eepr om-lik e memor y area. it can be used to store data which n eed t o be ret a ined in vba t an d sta ndb y mod e . this mem o r y ar ea is disab l ed b y d e f ault t o minimi z e po w e r con s u m pt ion ( see sect ion 3 .1 9: l o w- po w e r mo de s ). it ca n be e nab led b y so ft w a re . th e ba c k u p re gist ers ar e 32 -b it re gist er s used t o st or e 80 b yte s of user a p p lica t io n da ta when v dd po w e r is not pr esen t. ba c kup r egist er s ar e no t r e set b y a syst em, a po w e r re set , o r when t h e de vice w a k e s u p fr om t h e st an db y mo de ( s e e sect ion 3 . 1 9: l o w- po w e r mo de s ). ad dit i ona l 3 2 - b it reg i ste r s co nt ain t h e p r o g r a mm ab le ala r m subse c o nds , secon d s , m i n u t e s , h our s , d a y , an d da te . lik e b a c k up sr am , th e r t c an d ba c ku p re g i ste r s ar e su pp lie d thr o ug h a s wit ch th at is po w er ed eith er f r om t he v dd sup p ly wh en pr esen t or fr om t h e v ba t pin . 3. 19 lo w-po wer modes th e d e vices supp or t t h r e e lo w- po w e r mod e s to a c h i e v e t h e b e st comp ro mise be tw een l o w p o w e r co nsump t io n, sh or t st ar t up t i me an d a v a ilab l e w a k eup so ur ce s: sle e p mode i n sleep m ode , only t he cpu is st op ped . all per iphe r a ls co nt in ue t o op er a t e and ca n w a k e up t h e cpu whe n an in te rr u p t / e v ent occur s . stop mode the sto p mo de achie v e s t h e lo w e st po w e r co nsump t io n while re ta ining t he con t e n t s of sram a nd r egist er s . all cloc ks in t h e 1 . 2 v d o ma in ar e st op pe d, t h e pl l, t h e hsi rc and the hs e cr ystal osc illators are disab l ed. the v o ltage regulator can also be put either in nor m al or in lo w-po w e r mode . t h e d e vice ca n be wok e n up fr om t h e sto p m o d e b y a n y of th e e x ti line ( t he e x ti lin e sour ce ca n be o ne of t he 16 e xte r n a l lin es , t he pvd o u t put , t h e r t c ala r m / w a k e up/ ta m p e r / tim e st am p e v en ts , th e usb o t g fs/hs w a k e u p o r th e eth e r n et w a k e up ) . sta ndb y mode the st a ndb y m ode is used t o a c h i e v e t he lo w e st po w e r con s u m pt ion . th e int e r nal v o lt ag e re gula t o r is s wit ch ed o f f so t h a t t h e e n t i re 1 . 2 v d o ma in is po w e r ed of f . th e pll, the hsi rc and the hse cr y stal oscillators are also s witched off . after enter i ng
functional overview stm32f437xx 24/82 doc id 023139 rev 1 sta n d b y mod e , t he sram and r e g i st er co nt en ts ar e lost e x cep t f o r r e g i st er s in th e ba c k u p do main a nd t h e b a c k up sram wh en sele ct e d . the de vice e x it s t h e sta ndb y mod e when an e x t e r nal r e set (nrst pin) , an i w dg r e set , a r i sing e dge o n t he wkup pin , or an r t c alar m/ w a k e u p / t a mpe r /tim e st a m p e v en t occurs . the sta ndb y mo de is n o t su ppo r t e d whe n t h e emb edd ed v o lt age re gula t or i s b y passed an d th e 1. 2 v dom ain is co nt ro lled b y a n e x te r n a l po w e r . no te : w h e n in st an db y m o de , o n ly an r t c a l ar m / e v en t or a n e x t e r n al re se t ca n w a k e u p th e de vic e p r o v id ed v dd is su pplie d b y an e x t e r n a l b a t t e r y . 3. 20 v ba t operati o n th e v ba t pin a llo ws to p o w e r th e de vice v ba t d o m a in fro m a n e x ter n al ba tte r y , an e x t e r n a l sup e r c a pacit or , or f r o m v dd whe n no e x t e r nal ba tt e r y a n d a n e x t e r n al su pe rcap acito r ar e pr es en t. v bat ope r a t i on i s act i v a t ed whe n v dd is no t pr es en t . th e v ba t p i n su pp lies t h e r t c , th e ba c k u p re giste r s and th e bac ku p sram. not e : w he n t he micro cont r o ller is supp lied f r om v ba t , e xt e r n al int e r r up ts an d r t c ala r m/ e v e n t s d o not e xit it fr om v ba t ope r at i on . 3. 21 timer s and watc hdogs th e d e vices includ e t w o ad v anced -con t r ol t i me r s , eigh t g ene r a l- pu r p o se tim e rs , t w o b a sic tim e r s an d two w a tc hd og t i me rs . all t i mer cou n t e r s can b e f r oz en in d e b ug mo de . ta b l e 3 co mpa r e s t h e f e a t u r e s of t he ad v anced -con t r ol, ge ner al-p ur po se a nd b a sic t i mer s .
stm 32f4 3 7 x x functional overview doc id 0 2313 9 re v 1 25/82 3.21.1 ad v a nced-contr o l ti mer s (tim1, tim8) th e ad v anced -con tr ol t i mer s ( t i m 1, ti m8) ca n be see n as t h ree - p hase pwm ge ner at or s m u ltip le x ed o n 6 ch an nels . th e y ha v e co mple men t a r y pwm o u t p u t s wit h p r og r a mm ab le in se r t e d dea d t i mes . the y ca n also be con sider ed a s comp let e ge ner al- pur po se t i me rs . th eir 4 inde pen de nt cha n n e ls can be used f o r : in p u t ca pt ur e ou tp ut co mpa r e pwm g e n e r a tio n (e dge - or ce nt er -a ligne d mod e s) on e- pulse mo de o u t put i f co nf igu r e d a s st an dar d 1 6 - b it t i mer s , t h e y ha v e t h e sa me f e at ur es as t h e gen er a l -p ur pose timx timers . if c o nfigured as 16-bit pw m gener a tors , the y ha v e full modulation capability (0- 1 00%) . th e ad v anced -con tr ol t i mer ca n w o r k t oge t her wit h t he ti mx tim e r s via th e time r lin k f e a t u r e f o r synch r on izat ion or e v en t cha i ning . t a b l e 3. ti mer f eat ure c o mpar is on timer type time r counter re solution counter type pre scaler factor dma reques t g e ne rati on capture / c o mpar e ch a n n e l s c o mple mentar y ou tpu t max interface cl o c k (m hz ) ma x timer cl o c k (m hz ) (1) adv a nced- control tim 1 , ti m8 16-b i t up , do w n , up/do w n an y intege r betw e en 1 a nd 655 36 ye s 4 y e s 8 4 1 6 8 gener a l pu r p ose tim 2 , ti m5 32-b i t up , do w n , up/do w n an y intege r betw e en 1 a nd 655 36 y e s 4 n o 42 8 4 /168 tim 3 , ti m4 16-b i t up , do w n , up/do w n an y intege r betw e en 1 a nd 655 36 y e s 4 n o 42 8 4 /168 tim9 16-b i t u p an y intege r betw e en 1 a nd 655 36 no 2 no 8 4 1 6 8 tim10, ti m11 16-b i t u p an y intege r betw e en 1 a nd 655 36 no 1 no 8 4 1 6 8 tim12 16-b i t u p an y intege r betw e en 1 a nd 655 36 n o 2 n o 42 8 4 / 168 tim13, ti m14 16-b i t u p an y intege r betw e en 1 a nd 655 36 n o 1 n o 42 8 4 / 168 basic tim 6 , ti m7 16-b i t u p an y intege r betw e en 1 a nd 655 36 y e s 0 n o 42 8 4 /168 1. th e maximum timer clock is either 84 or 168 mhz dep endin g on t i mpre bit config u r ation in the r cc_dc kcfgr register.
functional overview stm32f437xx 26/82 doc id 023139 rev 1 t i m 1 an d ti m 8 s u p p o r t in de pe n d e n t dm a re qu e s t ge ne r a t i on . 3.21.2 general-purpose timers (timx) th er e ar e te n syn c h r o n izab le ge ner al- pur po se t i me rs emb edd ed in t h e stm 32f 43x de vices (s ee ta b l e 3 f o r diff erences). tim2, tim3, tim4, tim5 the stm3 2f4 3 x includ e 4 f u ll- f eat u r ed ge ner al-p ur po se tim e rs : ti m2, ti m5, t i m3, and ti m4 . t h e ti m2 an d ti m5 t i mer s a r e b a sed o n a 32- bit au to -r eloa d up /d o w n c o u n t e r an d a 16 -bit pr escaler . the ti m3 a n d t i m4 time rs ar e ba se d on a 1 6 -b it a u t o - r e l oad up /d o w n c o u n t e r an d a 16 -bit pr escaler . the y a ll f e a t ure 4 inde pen de nt cha n n e ls f o r inp u t ca pt ur e/ out pu t comp ar e , pwm or o ne- pu lse m ode out pu t. this giv e s up t o 16 inp u t ca pt ur e/ out pu t comp ar e/ pwm s o n th e lar gest p a c kag es . th e ti m2 , ti m3 , ti m4 , ti m 5 ge ne r a l- pu r p o se tim e rs ca n w o r k t o g e th e r , o r w i th th e ot he r ge ner al- pur po se t i me rs and th e adv a n ced - con t r o l t i mer s ti m1 a nd ti m8 via t h e t i m e r l i nk f e at ur e f o r s yn ch r on iza t ion or e v en t chain i ng . an y of t hese ge ne r a l- pur po se time rs ca n be u s e d t o gen er a t e pwm ou t put s . tim 2 , tim 3 , tim 4 , tim 5 a ll h a v e in de pe n d e n t dm a re qu e st ge ne r a t i on . th e y ar e capa b l e of h and ling q uad r a t u r e ( i ncre men t a l ) en co de r sig n a l s an d t he dig i t a l out pu t s f r om 1 t o 4 h a ll- ef f e ct sensor s . tim9, tim10 , t i m1 1, t i m 12, tim13 , an d t i m 1 4 the se tim e r s ar e ba se d on a 1 6 - b it a u t o - r e l oad upcou nt er a n d a 1 6 - b it p r e s cale r . ti m10 , ti m1 1, t i m 13, an d tim 14 f e a t u r e o ne in dep end en t chan ne l, wher ea s ti m9 a n d t i m 1 2 ha v e two in d e p e n d e n t ch an ne ls f o r in p u t ca pt ur e/ ou tp ut co m p a r e , pw m or o n e - p u l se m o d e ou tp u t. th e y ca n be sy nc hr on iz ed w i th th e ti m 2 , t i m 3 , t i m 4 , t i m 5 f u ll- f e at ur ed ge ne r a l- pur po se time rs . th e y ca n also be u sed as sim p le t i me b a ses . 3.21.3 basic timer s tim6 and tim7 th ese t i mer s a r e ma inly used f o r d a c t r igg e r a nd w a v e f o r m gen er a t io n. the y can a l so be u s e d as a gen er ic 16- bit tim e base . t i m 6 an d ti m 7 s u p p o r t in de pe n d e n t dm a re qu e st ge ne r a t i on . 3.21.4 independent watc hdog th e ind epe nd ent w a t chdo g is b a sed o n a 12 -bit do wncou n t e r a n d 8 - b i t pr escaler . it is cloc k e d f r o m an inde pe nde nt 32 khz int e r n al rc a n d as it o per at es inde pe nde nt ly fr om t h e ma in cloc k, it can ope r a t e in sto p an d st and b y mo de s . i t ca n be used eit her as a w a t c h dog t o r e set t he d e vice when a pr ob lem occu rs , o r as a f r ee- r u n n in g t i mer f o r a pplica t io n t i meo u t ma na gem ent . i t is ha rd w a r e - o r sof t w a r e -co n f i gur ab le th ro ug h th e opt io n b yt e s . 3.21.5 windo w watc hdog th e windo w w a t chdo g is b a sed o n a 7- bit d o wn c oun te r t hat can be se t as fr ee -r u nnin g . it can be u s e d as a w a tch dog to rese t t h e d e vice when a pr ob lem o ccu rs . i t is cloc k e d fr om t h e main cloc k. it has an ear l y w a r n ing interr up t capability and the counter c a n be froz en in d e b ug mo de .
stm32f437xx functional overview doc id 023139 rev 1 27/82 3.21.6 systic k timer th is t i me r is d e d i ca te d t o re al- t ime ope r a t i ng syste m s , b u t cou l d also be used a s a st and ar d d o wn co unt e r . it f eat ur es: a 2 4 - b it do wncoun te r a u toreload capability m a s ka b le sys te m int e r r up t ge ne r a t i on w h e n th e co un te r r e ach e s 0 pro g r a m m ab le cloc k so ur ce . 3. 22 inter - integrated ci r c uit in terface (i2c ) up t o th re e i 2 c b u s int e r f aces ca n ope r a t e in m u ltim aste r an d sla v e mo des . th e y ca n sup por t t h e sta nda rd - a nd f a st -m ode s . the y supp or t t he 7 / 10- bit ad dr essin g m ode an d t h e 7- bit d u a l a d d r ess i ng m o de ( a s sla v e) . a ha rd w a r e crc g e n e r a tio n / v er if ica t io n is e m be dde d. th e y can be se r v ed b y dm a a nd t h e y sup por t smbus 2 . 0/ pm bus . th e de vices also inclu de pr og r a mma b l e ana log a nd dig i t a l noise f ilt ers (se e ta b l e 4 ). 3. 23 uni ver sal sync hr onous/async hr onous receiver transmitter s (u sa r t ) t h e de v i ce s em be d f o ur u n iv e r s a l syn ch ro no u s/a sy nch r on ou s re ce iv er tr a n s m it te rs ( u sar t1 , usar t2 , usar t 3 and usar t6) and t w o univ e rsal asynchr ono us re ce iv er t r a n smit te rs (u ar t4, u a r t5, u a r t7 , an d u a r t8 ) . th ese six in te rf aces pr o vid e asyn chro no us co mm u n i ca tion , ird a s i r e ndec su pp o r t, m u ltip ro ce ssor co mm un ica t io n mo de , sing le- w ir e ha lf- d u p le x comm un icat ion mo de a nd ha v e lin master/sla v e capability . the usar t1 and u sar t6 interf aces are ab le to co mmun i ca te a t sp e e d s of up to 10 .5 m b it /s . t h e ot he r a v a ilab l e in te rf ac es co m m un ica t e a t up t o 5.2 5 b i t/s . usar t 1 , usar t2 , usar t3 an d usar t6 also p r o vide ha rd w a r e m ana gem ent o f t he ct s an d r t s s i gn a l s , sm ar t ca r d m o de ( i so 7 8 1 6 co m p lia nt ) an d spi- lik e co mm u n i cat i on ca pa b i lit y . all in te rf ac es ca n be s e r v ed b y t h e dm a con t r o lle r . t a b l e 4. compa r i s on of i2 c an al og and d i g i t a l fi lt er s ana l og filter digital filter pulse wid th o f suppr e ss ed spik es 50 ns pro g rammab l e l eng th from 1 to 15 i2 c p e r i p heral cloc ks bene fits a v ai lab l e in sto p mo de 1. extr a filter in g capab ility vs . stan dard req u iremen ts . 2. stab l e leng th dr a w bac ks v a r i ation s d epen din g o n temperature , v o l t a g e , p r o cess d i sa b le d wh en w a k e up f r om st op mo de is ena b l ed
fu nct i o n al ove r vi ew stm32f437xx 28/82 doc id 023139 rev 1 3. 24 serial peripheral interface (spi) th e de vices f eat ur e up t o six spi s in sla v e and mast er mo de s in f u ll- dup le x and simp le x com m u nicat i on m ode s . spi 1, spi 4 , spi5 , a nd spi6 ca n co mm un ica t e at u p to 42 m b its/ s , spi 2 an d spi 3 can com m unicat e a t up t o 2 1 m b it / s . th e 3- bit pre sca ler g i v e s 8 m a ste r mo de f r equ encie s an d th e f r ame is conf igu r ab le t o 8 bit s or 1 6 bit s . th e ha rd w a r e crc g ene r a t i on /v e r ifi c a t io n sup por t s ba sic sd car d / mmc mo des . all spi s ca n b e ser v ed b y t h e dma c o ntroller . th e spi int e rf ace can be co nf igur ed t o o per at e in ti m ode f o r co mm un ica t ions in mast er mo de a nd sla v e mod e . 3. 25 inter - integrated sound (i 2 s) t w o sta nda rd i 2 s int e r f a c e s ( m ult i ple x e d wit h spi 2 and spi 3 ) are a v a ilab l e . th e y ca n be o per at ed in ma ste r or sla v e mod e , in f u ll du ple x an d sim p le x comm un icat ion mo des , an d can b e conf igu r e d to ope r a t e with a 16- / 32- bit re so lut i on a s an in pu t or out pu t cha nne l. a u dio sa mpl i ng fr eq ue ncies f r o m 8 khz u p to 192 khz are sup p o r t e d. whe n e i t her o r bo th of t a b l e 5. usar t f e a t ure compa r i s on usar t name st andar d featur es modem (r ts/ c ts) lin spi ma ster ird a smar tcar d (iso 7 816 ) max . ba ud ra te in mb it/ s (o ver s a mpling by 1 6 ) max. baud rate in mb it/ s (o ve r s am p lin g by 8 ) apb mapping u s ar t1 x x x x x x 5.25 10.5 apb2 (m ax . 84 mhz) u s ar t2 x x x x x x 2.62 5.25 apb1 (m ax . 42 mhz) u s ar t3 x x x x x x 2.62 5.25 apb1 (m ax . 42 mhz) u a r t 4 x - x - x - 2 .62 5 .25 apb1 (m ax . 42 mhz) u a r t 5 x - x - x - 2 .62 5 .25 apb1 (m ax . 42 mhz) u s ar t6 x x x x x x 5.25 10.5 apb2 (m ax . 84 mhz) u a r t 7 x - x - x - 2 .62 5 .25 apb1 (m ax . 42 mhz) u a r t 8 x - x - x - 2 .62 5 .25 apb1 (m ax . 42 mhz)
stm32f437xx functional overview doc id 023139 rev 1 29/82 th e i 2 s int e r f a c e s is/ a re co nf igur ed in mast er mo de , t h e mast er cloc k ca n be o u t p u t t o th e e x t e r n a l d a c/ codec at 25 6 tim e s t h e sa mplin g fr eq uen cy . all i 2 sx ca n be ser v ed b y t h e dm a con t r o lle r . not e : f o r i 2 s2 f u ll- du ple x mo de , i 2 s2 _ck and i2 s2_ws signa ls can be u s e d on ly o n gpi o p o r t b an d g p io p o r t d . 3.26 a u dio pll (plli2s) th e de vices f eat ur e an a d d i tio nal d edicat e d pl l f o r a udio i 2 s applic ation. it allo ws to ac hie v e e r r o r - fr ee i 2 s sa mpli ng cloc k accu r a cy wit ho ut com p r o mising o n t he cpu p e r f o r ma nce , while u s in g usb pe r i phe r a ls . th e pll i 2 s con f ig ur a t io n can be m odi fie d to m ana ge a n i 2 s samp le r a t e chan ge wit ho ut d i sa b lin g t he ma in pll ( p ll) used f o r cpu , usb an d eth e r n et int e r f a c e s . th e au dio pll ca n be pr og r a mme d with v e r y lo w er ro r t o obt a i n sa mplin g r a t e s r a n g in g fr om 8 k h z to 1 9 2 khz. i n ad dit i on t o t h e a udio pl l, a mast er cloc k inpu t p i n ca n be u s e d t o synch r on iz e t h e i 2 s f l o w wit h an e x t er nal pll (or co de c ou tp ut ). 3. 27 secure digital input/ output interface (sdio) an sd/s dio/mmc hos t interf ac e i s a v ailab l e , th at su pp o r ts mu ltimediacard sy stem sp ecificat io n v e r s io n 4. 2 in t h r ee d i ff er en t da ta b u s m ode s: 1- bit ( d e f a u lt ), 4- bit and 8 - b i t. th e int e r f ace allo ws d a t a tr ansf e r a t up to 4 8 mhz, an d is comp lian t with t h e sd me mor y card spec ification v e rsion 2.0. th e sdio car d spe c if icat ion v e rsio n 2. 0 is a l so sup p o r t e d wit h t w o d i ff er en t da t a b u s mo de s: 1- bit ( d e f a u lt ) an d 4- bit . th e cur r en t v e r sion sup por t s o n ly one sd/ s di o/ mm c4 .2 car d at an y one t i me a nd a st ac k of m m c4. 1 or p r e vio us . i n ad dit i on t o sd/ s dio / m m c , th is in te rf ace is f u lly co mplia nt wit h th e ce- a t a d i git a l pr ot ocol re v1.1. 3. 28 ethernet ma c interface with dedicated dma and ieee 1588 suppor t the de vices pro v ide an ieee- 802.3-2002-comp liant media access controller (ma c ) f o r e t h e r n et lan comm u n icat ion s th ro ugh an indu str y - sta nd ard me dium -in dep end en t in te rf ace ( m i i ) or a r e d u ced me dium -in dep en den t int e rf ace (rmi i ) . the m i cr ocon tr olle r re qu ire s an e x te r n al ph ys ical int e r f a ce d e vic e (ph y ) t o co nn ec t t o the p h ysic a l l a n b u s ( t wis te d- pa ir , f i be r , et c. ) . th e phy is con nect e d t o t h e d e vice mii p o r t usin g 1 7 sig nals f o r mii or 9 sig n a l s f o r r m ii, an d ca n be c l oc k e d us ing th e 2 5 mh z ( m i i ) fr om t h e m i cr oc on tr olle r .
functional overview stm32f437xx 30/82 doc id 023139 rev 1 th e de vices includ e the f o llo wing f e a t u r e s : sup por t s 1 0 and 100 m b it /s r a t e s dedicat e d dma co nt ro ller a llo win g h i gh -spe ed t r ansf e r s be tw ee n t h e d edica te d sram an d th e de scr i pt o r s ( s ee t h e stm 32f 46x re f e re nce man u al f o r d e t a ils) t a gg ed m a c fr am e su p p o r t (vl a n su pp or t) half -d uple x ( c sm a/ cd) an d fu ll-d uple x o per at ion m a c con t r o l su b l a y er (c on tr ol fr am e s ) su pp o r t 32 -b it crc ge ner at ion an d re mo v a l se v e r a l ad dr ess filt er in g mo de s f o r ph ysical a n d m u lt ica s t a ddr ess (m ult i cast and g r o u p ad dr esse s) 32 -b it sta t u s cod e f o r ea ch tr a n smit t ed or re ce iv ed f r ame in te r n a l fifos to b u ff e r tr an sm it a n d r e c e iv e fr a m es . th e tr an sm it fifo a n d th e r e ceiv e fi fo ar e bo t h 2 kb yt es . suppor ts hardw a re ptp (pre cision time protocol) in accordance with ieee 1588 2008 ( p tp v2 ) w i th th e tim e sta m p co mp a r a t o r co nn ec te d to th e ti m 2 in p u t trigger s in te rr u p t whe n syst em t i me be come s g r eat er th an t a r get t i me 3. 29 contr o ller area netw ork (bxcan) th e tw o cans ar e co mplia nt with t h e 2. 0a and b ( a ct iv e) specif ica t ions wit h a b i tr at e u p to 1 mb it /s . the y ca n re ce iv e and tr a n smit st an dar d f r am es wit h 11 -bit ide n t i fie r s as w e ll as e x t e n d e d f r am es wi th 29- bit id ent if ier s . each can has t h r e e tr ansmit ma ilbo x e s , tw o r e ceiv e fi fo s wit h 3 st age s a nd 2 8 sh ar ed scala b l e f ilt er ban ks (a ll of t h em can b e used e v en if on e can is used). 256 b ytes of sra m are allocated f o r each can. 3. 30 uni ver sal serial b u s on -the-go full-speed (o tg_fs) th e de vices e m b e d a n usb o t g f u ll- spee d de vice/ h ost/ o t g p e r i p her al wit h in te g r at ed t r a n sce i v e rs . th e usb o t g f s pe r i ph er a l is co mpli ant wit h t h e usb 2 . 0 sp ecif ica t io n an d wit h th e o t g 1 . 0 spe cificat ion . i t h a s so ft w a re- conf ig ur a b le e ndp oin t set t in g an d su pp or t s su sp en d/ re su m e . t h e usb o t g fu ll-s p e e d c o n t r o lle r re qu ir es a de d i cat e d 4 8 m h z c l oc k that is gener a ted b y a pll connected to the hse osc illato r . the major f eatures are: comb ined rx and t x fi fo siz e o f 32 0 3 5 bit s wit h dyna mic fi fo sizing sup por t s t h e session r e q uest pro t o col (srp) an d ho st neg ot iat i on p r o t o c o l (hnp) 4 bid i re ct ion a l en dpo int s 8 ho st chan nels with p e r i o d ic o u t sup p o r t hnp/ snp/ i p in side ( no ne ed f o r a n y e xt e r nal r e sist o r ) f o r o tg/ host m ode s , a p o w e r s wit ch i s ne ede d in case b u s-p o w e r ed d e vice s a r e conn ect e d 3. 31 uni ver sal serial b u s on-the-go hi gh-speed (o tg_hs) t h e de v i ce s e m be d a usb o t g h i gh -s pe ed ( u p t o 48 0 m b/ s) de vice /h o st/o t g p e r i p h e r a l. th e usb o t g hs su pp or t s bo th f u ll-spe ed an d hig h - s p eed o p e r at ion s . i t in te g r at es t he t r a n sce i v e rs f o r fu ll-spe ed op er at io n ( 1 2 m b/ s) and f e a t u r e s a utm i lo w- pin int e rf ace (ulpi )
stm32f437xx functional overview doc id 023139 rev 1 31/82 f o r high -spe ed o per a t ion ( 480 m b / s ). when u s in g t he usb o t g hs in hs m ode , an e x t e r n a l phy d e vice co nn ecte d to th e ul pi is r e q u ir ed. the usb o t g hs per i pher a l is compliant with the usb 2.0 sp ec if ica t io n an d with t h e o t g 1 . 0 spe cificat ion . i t h a s so ft w a re- conf ig ur ab le e ndp oin t set t in g an d su pp or t s su sp en d/ re su m e . t h e usb o t g fu ll-s p e e d c o n t r o lle r re qu ir es a de d i cat e d 4 8 m h z c l oc k that is gener a ted b y a pll co nnected to the hse osc illator . t h e m a jo r f e at ur es a r e : co m b in e d rx a n d tx f i f o siz e of 1 kb it 35 w i th dy na m i c f i f o siz i ng sup por t s t h e session r e q uest pro t o col (srp) an d ho st neg ot iat i on p r o t o c o l (hnp) 6 bid i re ct ion a l en dpo int s 12 h o st cha nne ls wit h per iodic out su pp or t in te r n a l fs o t g phy su pp o r t ext e r n a l hs or hs o t g op er a t io n supp or t i ng ulpi i n sdr mod e . t he ot g phy is co n n e cte d to t h e m i cr oc on tr olle r ulp i p o r t t h r o ug h 12 s i gn als . i t ca n b e cloc ke d us in g t he 60 m h z ou tp ut . in te r n a l us b dm a hnp/ snp/ i p in side ( no ne ed f o r a n y e xt e r nal r e sist o r ) f o r o t g / h o s t mod e s , a po w e r s w it ch is n e e ded in ca se b u s- po w e re d de vices ar e conn ect e d 3. 32 digital camera interface (dcmi) th e de vices emb e d a cam e r a in te rf ace t h a t can con nect wit h came r a mo dule s a nd cmos sen s o r s th ro ugh an 8- bit to 1 4 - b it par a llel int e r f ace , t o re ce iv e vid e o d a t a . t he came r a in te rf ace can sust ain a d a t a tr ansf e r r a t e up to 54 mb yt e/ s a t 54 mhz. it f e at ur es: pro g r a m m ab le po lar i t y f o r th e inpu t p i x e l clo c k an d syn c h r o n izat ion sign als p a r a lle l dat a comm u n icat ion can b e 8- , 1 0 -, 12 - or 1 4 - b it sup por t s 8 - b i t pr og r e ssiv e vid eo mo no ch ro me or r a w ba y e r f o r m at , ycbcr 4 : 2 : 2 pr og r e ssiv e vid e o , rg b 5 65 pr og r e ssiv e vid eo o r co mpr e ssed d a t a (lik e jpeg) sup por t s con t in u o u s mo de or sn ap sh ot ( a single fr a m e) mod e capability to automati cally c r op the image 3. 33 cr yptographic acceleration th e d e vices emb e d a cr yp to g r ap hic acce ler a to r . th is cr ypt o g r aph ic a c cele r a t o r pr o v id es a set of h a r d w a re a c ce ler a t i o n f o r t he ad v ance d cr ypt o g r a phic alg o r i t h ms usua lly ne ed ed t o
functional overview stm32f437xx 32/82 doc id 023139 rev 1 p r o v ide con f id en tia lity , au t hen ticat i o n , d a t a int e g r it y and n on r epu dia t io n when e x ch ang ing m e ss ag e s wit h a pe er . the s e algo r i t h ms co nsist s of : encr yption/d ec r y ption ? d es/ tdes ( dat a e n cr ypt i on st an dar d/ t r iple d a t a encr y p t i on sta n d a rd ): ecb (ele ctr o n i c code bo ok) an d cbc (ciph e r b l oc k chain i ng ) ch ain i ng a l gor it hm s , 6 4 - , 128 - or 192 -b it k e y ? a es (a dv an ced en cr ypt i on st and ar d) : ecb , cbc , gcm, ccm, a n d ct r (co unt er mod e ) cha i ning a l go r i th ms , 128 , 19 2 or 256 -b it k e y univ ersal hash ? s ha- 1 and sha- 2 ( secur e ha sh a l go r i th ms) ?m d 5 ?h m a c th e cr ypt o g r aph ic accele r a t o r su ppo r t s dm a r e q uest g e n e r a tio n . 3. 34 random n u mber g e nerator (rng) all d e vices em bed a n rng t h at d e liv er s 3 2 - b it r and om n u mbe r s gen er a t e d b y an in t e g r a t e d a nalo g circuit . 3. 35 general-purpose input/outputs (gpios) ea ch o f t he g p i o p i ns ca n be con f ig ur ed b y sof t w ar e as out pu t ( push - pu ll or o pen -d r a in , wit h or wit ho ut p u ll- up or pull- do wn) , a s inp u t (f loating, with or w i thou t pull-up or pull-do wn) o r as per ip he r a l alt e r nat e f u n c t i on . mo st of th e gpi o pin s ar e sha r ed wit h dig i ta l or a nalo g a l te r n a t e fu nctio n s . all g p io s a r e h i gh- curr en t- capa b l e and h a v e sp eed se lectio n to bet t e r ma na ge int e r n a l n o ise , po w e r con sump t io n and elect r o m ag net ic e m ission. th e i / o con f igur at ion can b e loc k e d if ne ed ed b y f o llo wing a spe cific se que nce in or de r t o a v oid spu r iou s wr itin g t o the i / o s r egist er s . f a st i / o han dlin g allo wing ma xim u m i/ o t o g g lin g up t o 84 m h z. 3. 36 analog-to-digital con v er ter s (adcs) th re e 12 -bi t an alog -t o- dig i ta l co n v e r t e rs a r e e m be dd ed an d ea ch adc sha r e s u p to 1 6 e x te r n al ch an n e ls , pe rf or m i ng co n v e r sion s in the s i ng le -sh o t o r sca n mo d e . i n sca n m o d e , a u t o ma tic con v e r sion is pe rf or med o n a select ed g r ou p of a n a l og inp u t s . ad dit i ona l lo gic fu nct i ons emb edd ed in t h e adc int e r f a c e a llo w: sim u lt an eou s samp le an d hol d i n t e r l ea v e d sa mple a nd h o ld th e adc can be se r v ed b y th e dm a con t r o lle r . an an alo g w a t chdo g f eat ur e allo ws v e r y p r e c ise mo nit o r i n g of t h e co n v e r t e d v o lt age o f o n e , some or a ll sele ct e d ch ann els . an in te rr u p t is ge ner at ed whe n th e co n v e r te d v o lt ag e is ou tsid e th e pr og r a mme d th re sh olds . t o synchr on iz e a/ d con v er sio n an d tim e rs , t he adcs could b e t r igge re d b y an y of t i m1 , ti m2 , ti m3 , ti m4 , ti m5, or t i m 8 tim er .
stm32f437xx functional overview doc id 023139 rev 1 33/82 3. 37 t e mperature sensor th e t e m per at ur e sen s o r h a s t o ge ne r a t e a v o lt age t hat v a r i es line a r l y wi th te mpe r at ur e . the con v er sion r a nge is be tw een 1. 8 v a nd 3. 6 v . t he t e mp er a t u r e sen s o r is in t e r n ally con nect e d t o t h e adc1_i n16 in put ch an nel which is u s e d t o co n v e r t t he sen s o r ou tp ut v o l t age into a digital v a lue . as th e of f s e t o f t he t e mp er a t ure se nsor v a r i es fr om chip t o chip due t o p r o c e s s v a r i a t io n, t h e in te r n a l te mpe r at ur e sensor is ma inly su ita b le f o r ap plicat ions t hat det e c t te mpe r at ur e cha nge s in st ea d of absol ut e te mpe r at ur es . i f an a c cu r a t e t e mp er a t u r e r ead ing is ne ede d, t h e n an e x t e r nal t e m per a t ure se nsor p a r t sho u ld b e used . 3. 38 digital -to-analog con v er ter (d a c ) th e t w o 12 -b it b u f f er ed d a c ch an nels ca n be u s e d t o co n v e r t t w o dig i t a l sig n a l s int o t w o a nalo g v o lt ag e sig n a l o u t put s . th is d ual di git a l in te rf ace sup por t s t h e f o llo win g f e at ur es: t w o d a c co n v e r te rs: o ne f o r e a ch ou tp ut ch ann el 8- bit or 1 2 -b it mo no to nic o u t p u t le ft or r i g h t da ta a lig nm e n t in 12 -b it mo d e sy nc hroniz ed update capability no ise - w a v e g ene r a t i on tr ia n g u l ar -w a v e ge ne r a t i on du al d a c ch ann el ind epe nde nt or sim u lt an eou s con v er si ons dma capability f o r each c h annel e xt e r n al t r igge rs f o r con v er sio n in pu t v o lt ag e re f e re n ce v ref+ eig h t d a c t r igge r inp u t s a r e u s e d in t he de vice . the d a c chan ne ls ar e t r igge re d th ro ug h t h e t i me r up dat e o u t put s th at a r e a l so co nne ct e d to d i ff er en t dma st r eam s . 3. 39 serial wire jt a g deb u g por t (swj-dp) th e arm swj-dp int e r f a c e is em bed ded , a nd is a co mbin ed jt a g an d se r i al wire d e b u g p o r t t h a t en ab les eit h e r a ser i al wire d e b u g o r a jt a g pr ob e to b e conn ect ed t o th e t a rg et . deb u g is pe rf or med using 2 p i ns on ly inste a d of 5 r e q u ir ed b y t h e jt a g ( j t a g pin s co uld be r e- us e as gpi o wit h a l te r na t e fu nc tio n) : t h e jt a g tm s a nd tck pins ar e sh ar ed wit h swdio a nd swcl k, r e spect i v e ly , an d a sp ecif ic sequ en ce o n th e tms pin is used t o s w it ch b e t w ee n jt a g - d p an d sw - d p . 3. 40 embed d ed t r ace macr ocell? the arm embedded t r ace ma c r ocell pro vides a g r eater visib ility of the instr u ction and data f l o w in sid e t he cpu cor e b y str eam ing com p re sse d dat a a t a v e r y h i gh r a te f r om t he stm 32f 43x th ro ugh a sm all n u mb er o f etm pin s t o an e xte r n a l h a r d w a re t r a c e p o r t a nalyz e r (t p a ) de vice . th e tp a is conn ecte d t o a ho st co mpu t e r using usb , eth e r n et , o r a n y ot he r hig h - s p eed ch ann el. re al- t im e instr u ctio n and dat a f l o w act i vity ca n be r e cor d e d
functional overview stm32f437xx 34/82 doc id 023139 rev 1 a nd t h e n f o r m a t t e d f o r displa y on t h e host co mpu t e r t hat r uns t he de b u gg er sof t w ar e . tp a h a r d w a re is co mmer cially a v a ilab l e fr om com m on d e v e lo pme n t t o ol v e nd or s . the embedded trace macrocell operates with third party debugger software tools.
stm32f437xx pinouts and pin description doc id 023139 rev 1 35/82 4 pinouts and pin description fi gu re 8. stm 32f 43x l q fp1 00 pi nou t 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pe2 pe3 pe4 pe5 pe6 vba t pc14 pc15 vss vdd ph0 nrst pc0 pc1 pc2 pc3 vd d vssa vref+ vdd a pa 0 pa 1 pa 2 vdd vss vcap_2 p a 13 p a 12 pa 11 p a 10 p a 9 p a 8 pc9 pc8 pc7 pc6 p d 15 p d 14 p d 13 p d 12 pd 1 1 p d 10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss vdd pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe1 1 pe12 pe13 pe14 pe15 pb10 pb1 1 vcap_1 vdd vdd vss pe1 pe0 pb9 pb8 boo t0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc1 1 pc10 p a 15 p a 14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai18495c lqfp100 pc13 ph1
pinouts and pin description stm32f437xx 36/82 doc id 023139 rev 1 figure 9. stm32f43x lqfp144 pinout v dd pdr_on pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pg15 v dd v ss pg14 pg13 pg12 pg11 pg10 pg9 pd7 pd6 v dd v ss pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa 15 pa 14 pe 2 v dd pe 3 v ss pe 4 pe 5 pa 1 3 pe 6 pa 1 2 vb a t pa 1 1 pc 13 pa 1 0 pc 14 pa 9 pc 15 pa 8 pf0 pc 9 pf1 pc 8 pf2 pc 7 pf3 pc 6 pf4 v dd pf5 v ss v ss pg 8 v dd pg 7 pf6 pg 6 pf7 pg 5 pf8 pg 4 pf9 pg 3 pf1 0 pg 2 ph0 pd 1 5 ph1 pd 1 4 nr st v dd pc 0 v ss pc 1 pd 1 3 pc 2 pd 1 2 pc 3 pd 1 1 v ss a pd 1 0 v dd pd 9 v re f + pd 8 v dd a pb 15 pa 0 pb 14 pa 1 pb 13 pa 2 pb 12 pa 3 v ss v dd pa 4 pa 5 pa 6 pa 7 pc 4 pc 5 pb 0 pb 1 pb 2 pf1 1 pf1 2 v dd pf1 3 pf1 4 pf1 5 pg 0 pg 1 pe 7 pe 8 pe 9 v ss v dd pe 10 pe 11 pe 12 pe 13 pe 14 pe 15 pb 10 pb 11 v cap_1 v dd 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 lqfp144 120 11 9 11 8 11 7 11 6 11 5 11 4 11 3 11 2 111 11 0 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai18496b v cap_2 v ss
stm32f437xx pinouts and pin description doc id 023139 rev 1 37/82 fi gu re 10 . s tm 32f 43x l q fp1 76 pi nou t ms19916v2 pdr_on v dd pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pg15 v dd v ss pg14 pg13 pg12 pg11 pg10 pg9 pd7 pd6 v dd v ss pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pi7 pi6 pe2 v dd pe3 v ss pe4 pe5 p a13 pe6 p a12 vba t pa 11 pi8 p a10 pc14 pa 9 pc15 pa 8 pf0 pc9 pf1 pc8 pf2 pc7 pf3 pc6 pf4 v dd pf5 v ss pg8 pg7 pf6 pg6 pf7 pg5 pf8 pg4 pf9 pg3 pf10 pg2 ph0 pd15 ph1 pd14 nrst v dd pc0 v ss pc1 pd13 pc2 pd12 pc3 pd1 1 pd10 pd9 vref+ pd8 pb15 pa 0 pb14 pa 1 pb13 pa 2 pb12 pa 3 byp ass_reg v dd pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pf1 1 pf12 vss v dd pf13 pf14 pf15 pg0 pg1 pe7 pe8 pe9 v ss v dd pe10 pe1 1 pe12 pe13 pe14 pe15 pb10 pb1 1 v cap_1 v dd 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 132 131 130 129 128 127 126 125 124 123 122 121 120 11 9 11 8 11 7 11 6 11 5 11 4 11 3 11 2 111 11 0 109 108 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 80 lqfp176 152 151 150 149 148 147 146 145 144 143 142 69 70 71 72 73 74 75 76 77 78 79 26 27 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 99 98 89 v cap_2 pi4 p a15 p a14 v dd v ss pi3 pi2 pi5 140 139 138 137 136 135 134 133 ph4 ph5 ph6 ph7 ph8 ph9 ph10 ph1 1 88 81 82 83 84 85 86 87 pi1 pi0 ph15 ph14 ph13 v dd v ss ph12 96 95 94 93 92 91 90 97 37 38 39 40 41 42 43 44 pc13 pi9 pi10 pi1 1 vss ph2 ph3 vdd vss vdd vdda vssa vdda
pinouts and pin description stm32f437xx 38/82 doc id 023139 rev 1 fi gu re 11 . s tm 32f 43x ufbga1 76 ba ll out ai18497b 1 2 3 9 10 11 12 13 14 15 a p e 3 p e 2 pe 1 p e 0 p b 8 p b 5 p g14 p g13 pb 4 p b 3 p d7 p c 12 p a 15 p a 14 p a 13 b p e 4 p e 5 pe 6 p b 9 p b 7 p b 6 p g 1 5p g 12p g 1 1p g 1 0 p d 6 p d 0 p c 1 1 p c 1 0 p a 1 2 cv ba t p i 7 p i 6 p i 5 pdr_on vd d vd d v d d vd d p g 9 pd 5 p d 1 p i 3 p i2 p a 1 1 d p c 13 p i 8 pi 9 p i 4 bo o t 0 v s s vs s v s s pd 4 p d 3 p d 2 p h 1 5 p i1 p a 1 0 e pc 14 pf 0 p i1 0 p i1 1 ph1 3 p h 1 4 p i 0 p a 9 f p c 15 v s s vd d p h 2 vs s v s s vs s v s s vs s v ss vc a p _2 pc 9 p a 8 g ph 0 vs s v dd p h 3 v s s vs s v s s vs s v s s v ss v d d pc 8 p c 7 h ph 1 pf 2 pf 1 p h 4 vs s vs s v s s vs s v s s v ss vd d pg 8 p c 6 j nr s t p f 3 p f 4 ph 5 v ss v ss v ss v s s v ss vd d v d d p g 7 p g 6 kp f 7 p f 6 p f 5 vd d vs s v s s vs s v s s vs s p h 1 2 p g 5 pg 4 p g 3 lp f 1 0 p f 9 p f 8 byp ass_ reg ph 1 1 p h 1 0 pd1 5 pg 2 m v s s a p c 0 p c 1 p c2 p c 3 pb 2 p g 1 vss vss v c ap _1 p h 6 p h8 p h 9 p d14 p d13 nv r e f - p a 1 pa 0 pa4 pc 4 pf 1 3 pg 0 vd d vd d v dd pe 1 3 ph 7 pd 1 2 pd 1 1 pd 10 p v r e f + pa2 p a 6 pa5 p c 5 pf 1 2 pf 1 5 pe 8 pe 9 pe 1 1 pe 1 4 pb 1 2 p b 1 3 pd 9 p d 8 r v dd a p a 3 p a 7 p b 1 p b 0 p f11 p f14 pe 7 p e 10 p e 1 2 p e 1 5 pb 10 p b 11 p b 14 p b 15 vss 4 3567 8 t a b l e 6. le g e nd/abbrev iat i o n s us ed in t h e pino ut t a b l e name abbre v iation definition pin na me un less otherwi se sp ecified in b r ac k e ts belo w the pi n name , the pi n fun cti on dur i ng an d a f ter re se t is th e same as the a c tua l pin na me pin type s s upp ly pin i i npu t only p i n i/o i np ut/ outpu t pi n i/o str u cture f t 5 v toler a nt i / o tt a 3 .3 v tolerant i/o di rectl y con nected to ad c b dedicated boo t 0 p in rst b id irectiona l re set p i n with embed ded w eak pul l-up resistor notes u n l ess otherwi se sp ecified b y a note , a ll i/os a r e se t as fl oating in puts dur in g and after re set alter nate fu nctions functio n s se lected th roug h gpiox_afr re gisters additio nal fu nctions functio n s d i rectly se lected/ena b l e d through pe r ipher a l re gisters
stm32f437xx pinouts and pin description doc id 0 2313 9 re v 1 39/82 t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o str u cture notes alternate functions a d d itional f u nct i ons lq fp100 lq fp144 ufb g a1 76 lq fp176 1 1 a2 1 pe2 i/o f t tra c eclk , fsmc_a23, eth_mii_txd3, e vent o ut , spi4_sck 2 2 a1 2 pe3 i/o f t tra c ed0 , fsmc_a1 9 , e vent o ut , spi4_nss 3 3 b1 3 pe4 i/o f t tra c ed1 , fsmc_a2 0 , dcmi_d4, e vent o ut , sp i4_nss 4 4 b2 4 pe5 i/o f t tra c ed2 , fsmc_a2 1 , t i m 9 _ c h 1 , d c mi _d 6, eve nt out , s p i 4_m i so 5 5 b3 5 pe6 i/o f t tra c ed3 , fsmc_a2 2 , t i m 9 _ c h 2 , d c mi _d 7, eve nt out , s p i 4_m o si 66 c 1 6 v ba t s -- d 2 7 p i 8 i / o f t (2)(3) event o ut rtc_tamp1 , rtc _ tamp2, rtc_ts 77 d 1 8 p c 1 3 i / o f t (2) ( 3) event o ut r t c_ o u t , rt c _ t a mp1 , rtc_ts 88 e 1 9 pc14 /osc32_in (pc14) i/ o f t (2)(3) event o ut osc32_in (4) 99 f 1 1 0 pc15 /osc32_ out (pc15) i/ o f t (2)(3) event o ut osc32_out (4) - - d3 11 pi9 i /o ft can1_rx, event o ut - - e3 12 pi10 i/o f t et h_ mi i_r x _e r, event o ut - - e4 13 pi11 i/o f t o t g_hs_ul p i_ dir , event o ut -- f 2 1 4 v ss s -- f 3 1 5 v dd s -1 0 e 2 1 6 p f 0 i / o f t f s mc _a 0, i2 c 2 _sd a , event o ut -1 1 h 3 1 7 p f 1 i / o f t fsmc _a1 , i2c2 _scl , event o ut -1 2 h 2 1 8 p f 2 i / o f t fsmc_a2 , i2 c2_smba, event o ut - 1 3j 21 9 p f 3 i / o f t (4) fsmc_a3, event o ut adc3_in9 - 1 4j 32 0 p f 4 i / o f t (4) fsmc_a4, event o ut adc3_in14
pinouts and pin description stm32f437xx 40/82 doc id 023139 rev 1 -1 5 k 3 2 1 p f 5 i / o f t (4) fsmc_a5, event o ut adc3_in15 10 1 6 g2 22 v ss s 11 1 7 g3 23 v dd s -1 8 k 2 2 4 p f 6 i / o f t (4) t i m 1 0_ch1, fsmc_nio rd , event o ut , s p i5_nss , ua r t 7 _ r x adc3 _in4 -1 9 k 1 2 5 p f 7 i / o f t (4) tim11 _ ch1, fsmc_ nreg, event o ut , s p i5_sck, u a r t 7_tx adc3 _in5 - 2 0l 32 6 p f 8 i / o f t (4) tim13 _ ch1, f s m c _nio w r , eve nt out , s p i 5_m i so adc3 _in6 - 2 1l 22 7 p f 9 i / o f t (4) tim14_ ch1 , fsmc_cd , eve nt out , s p i 5_m o si adc3 _in7 - 2 2l 12 8 p f 1 0 i / o f t (4) fsmc_intr, e vent o ut , dc mi_d1 1 adc3 _in8 12 2 3 g1 29 ph0/ osc_in (ph0) i/o f t ev ent o ut osc_in (4 ) 13 2 4 h1 30 ph1 / osc _ ou t (ph1) i/o f t event o ut osc_out (4) 1 4 25 j1 3 1 nrst i /o rst 15 2 6 m2 32 pc0 i /o f t (4) ot g _ h s _ u l p i _ s t p , event o ut adc 123_ in1 0 16 2 7 m3 33 pc1 i /o f t (4) eth_mdc , e vent o ut adc 123_ in1 1 17 2 8 m4 34 pc2 i /o f t (4) spi2_miso , o t g_hs_ul p i_ dir , th_mii_txd2, i 2 s2e xt_sd , event o ut adc 123_ in1 2 18 2 9 m5 35 pc3 i /o f t (4) spi 2_mo si/i2s 2 _sd , o t g_hs_u lpi_ nxt , et h_m ii_t x _clk , event o ut adc 123_ in1 3 19 3 0 g3 36 v dd s 20 3 1 m1 37 v ss a s -- n 1 - v re f ? s 21 3 2 p1 38 v ref+ s 22 3 3 r1 39 v dd a s t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
stm32f437xx pinouts and pin description doc id 023139 rev 1 41/82 23 3 4 n3 40 pa 0 / w k u p (p a0) i/ o f t (5) usar t2_cts , u a r t 4_ tx, eth_mii_cr s , tim2 _ch1_ e tr , t i m5_ ch1 , ti m8 _etr , event o ut adc 123 _in 0 , w k u p (4 ) 24 3 5 n2 41 p a 1 i /o f t (4) usar t2 _r ts , u a r t 4 _ rx, eth_r m ii_ref_ clk, eth_mii_ rx_clk, tim5_ch2, timm2_c h2, event o ut adc12 3_in1 25 3 6 p2 42 p a 2 i /o f t (4) usar t2_tx, tim5_c h3, tim9_ ch1 , tim2 _ch3 , e t h_mdio , event o ut adc12 3_in2 - - f4 43 ph2 i /o ft eth_mii_crs , event o ut - - g4 44 ph3 i /o f t et h_mi i_col, e vent o ut -- h 4 4 5 p h 4 i / o f t i2c2 _scl, o t g_hs_u lpi_ nxt , event o ut -- j4 4 6 p h 5 i / o f t i2c2_sd a , event o ut , sp i5_nss 26 3 7 r2 47 p a 3 i /o f t (4) usar t2 _rx, tim5 _ch4 , tim9_ ch2 , tim2 _ch4 , o t g_hs_ulpi_d0, eth_mii_col, e vent o ut adc12 3_in3 27 3 8 - - v ss s l4 48 byp a ss_reg i ft 28 3 9 k4 49 v dd s 29 4 0 n4 50 p a 4 i /o tt a (4) spi1_nss , spi3_nss , usar t2_ck, dcmi_hsync , o t g_hs_sof , i2s3_ws , event o ut adc12_ in 4, d a c1_out 30 4 1 p4 51 p a 5 i /o tt a (4) spi1_sck, o t g_hs_ul p i_ ck, tim2 _ch1_ e tr , tim8_c hin, even t o ut adc12_ in 5, d a c2_out 31 4 2 p3 52 p a 6 i /o f t (4) sp i1_m iso , tim8_bkin , tim13 _ ch1 , dcmi_ pixcl k , tim3_ ch1 , ti m1_bk i n , event o ut adc12_ in6 t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
pinouts and pin description stm32f437xx 42/82 doc id 023139 rev 1 32 4 3 r3 53 p a 7 i / o f t (4) s p i1_m osi, t i m8_ch1n , tim1 4_ch 1 , tim3_ ch2 , eth_mii_rx_d v , tim1_ch1 n , rmii_crs_d v , event o ut adc12_ in7 33 4 4 n5 54 pc 4 i /o f t (4) eth_rmii_ r x_d0, eth_mii_ rx_d0, event o ut adc12 _ in14 34 4 5 p5 55 pc 5 i /o f t (4) eth_rmii_ r x_d1, eth_mii_ rx_d1, event o ut adc12 _ in15 35 4 6 r5 56 pb0 i / o f t (4) tim3_c h3, tim8 _ch2n , o t g_hs_ulpi_d1, eth _ mii_rxd2 , tim1_ ch2n , event o ut adc12_ in8 36 4 7 r4 57 pb1 i / o f t (4) tim3_c h4, tim8 _ch3n , o t g_hs_ulpi_d2, eth _ mii_rxd3 , tim1_ ch3n , event o ut adc12_ in9 37 4 8 m6 58 pb2/b oo t1 (pb2) i/o f t event o ut -4 9 r 6 5 9 p f 1 1 i / o f t dcmi_12, event o ut , spi5_mosi - 5 0 p 6 6 0 p f12 i /o ft fsmc_a6, event o ut - 5 1m 86 1 v ss s -5 2 n 8 6 2 v dd s - 5 3 n 6 6 3 p f13 i /o ft fsmc_a7, event o ut - 5 4 r 7 6 4 p f14 i /o ft fsmc_a8, event o ut - 5 5 p 7 6 5 p f15 i /o ft fsmc_a9, event o ut - 5 6 n 7 6 6 p g0 i/o f t f sm c_a10, e vent o ut - 5 7 m 7 6 7 p g1 i/o f t f sm c_a11, e vent o ut 38 5 8 r8 68 pe7 i / o f t fsmc_d4 , tim1_etr , event o ut , u a r t 7_rx 39 59 p8 69 pe8 i/o f t fsmc_d5, tim1_c h1n, event o ut , u a r t 7_tx 40 60 p9 70 pe9 i/o f t fsmc_d6 , tim1_c h1 , event o ut - 6 1m 97 1 v ss s -6 2 n 9 7 2 v dd s t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
stm32f437xx pinouts and pin description doc id 023139 rev 1 43/82 41 6 3 r9 73 pe1 0 i /o f t fsmc_d7, tim1_c h2n, event o ut 42 64 p10 7 4 pe11 i /o ft fsmc_d8 , tim1_c h2 , e vent o ut , spi4_nss 43 65 r10 7 5 pe12 i /o ft fsmc_d9, tim1_c h3n, e vent o ut , spi4_sck 44 66 n11 7 6 pe13 i /o ft fsmc_ d 10 , ti m1_ch3, eve nt out , s p i 4_m i so 45 67 p11 7 7 pe14 i /o ft fsmc_ d 11 , ti m1_ch4, eve nt out , s p i 4_m o si 46 68 r11 7 8 pe15 i /o ft fsmc_ d 12 , ti m1_bki n, event o ut 47 69 r12 7 9 pb10 i /o ft spi2_sck/i2s2_ck , i2c2_ s cl, u s ar t3_tx, o t g_hs_ulpi_d3, et h_ mi i_r x _e r, tim2_ch3, event o ut 48 70 r13 8 0 pb11 i /o ft i2c 2_sd a , u s ar t3_rx , o t g_hs_ulpi_d4, eth_rmii_tx_en, eth_mii_ tx_en, tim2_ch4, event o ut 49 7 1 m1 0 8 1 v cap_1 s 50 7 2 n 1 0 82 v dd s -- m 1 1 8 3 p h 6 i / o f t i2c2_smba, tim12_ ch1 , eth _ mii_rxd2 , event o ut , s pi5_sck, dcmi_d8 - - n12 8 4 p h7 i/o f t i2 c3_scl , eth_ mii_rxd3 , event o ut , spi5_miso , dcmi_d9 -- m 1 2 8 5 p h 8 i / o f t i2c3_sd a , dcm i _hs y nc , event o ut -- m 1 3 8 6 p h 9 i / o f t i2c3 _smba, tim12_ ch2, dcmi_d0, event o ut -- l 1 3 8 7 p h 1 0 i / o f t tim 5 _ c h 1 , d c mi _d 1, event o ut -- l 1 2 8 8 p h 1 1 i / o f t tim 5 _ c h 2 , d c mi _d 2, event o ut t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
pinouts and pin description stm32f437xx 44/82 doc id 023139 rev 1 -- k 1 2 8 9 p h 1 2 i / oft tim 5 _ c h 3 , d c mi _d 3, event o ut -- h 1 2 9 0 v ss s -- j1 2 9 1 v dd s 51 73 p12 9 2 pb12 i /o ft spi2_nss/i2s2_ws , i2 c2_smba, usar t3_ck , tim1_bkin, can 2_rx , o t g_hs_ulpi_d5, eth_rmii_ t xd0 , eth_mii_txd0, o t g_ hs _i d , ev en t o ut 52 74 p13 9 3 pb13 i /o ft spi2_sck ,/i2 s 2_ck, usar t3_cts , tim1_c h1n , can2_tx, o t g_hs_ulpi_d6, eth_rmii_ t xd1 , eth_mii_txd1, event o ut ot g _ h s _ v b u s 53 75 r14 9 4 pb14 i /o ft s p i2_m iso , t i m1_ch2n , tim1 2_ch1 , o t g_ hs_dm, usar t 3 _r ts , ti m8_ch2n, i2s2e xt_sd , ev ent o ut 54 76 r15 9 5 pb15 i /o ft spi 2_mo si/i2s 2 _sd , tim1_c h3n, tim8 _ch3 n, tim1 2_ch2 , o t g_hs_dp , event o ut , rtc_refin 55 7 7 p1 5 9 6 p d 8 i /o f t fsmc_d13, u sar t3_ t x, event o ut 56 7 8 p1 4 9 7 p d 9 i /o f t fsmc_ d 14 , u sar t3_r x, event o ut 5 7 79 n15 9 8 p d1 0 i /o ft fsmc_ d 15 , u sar t3_c k, event o ut 5 8 80 n14 9 9 p d1 1 i /o ft f s mc_ c le, fsmc _a 16 , u sar t3_ c ts , event o u t 5 9 81 n13 100 pd1 2 i/o f t fsmc_al e , fsmc_a1 7 , t i m4_ch1, u sar t3_r ts , event o ut 6 0 82 m15 101 pd1 3 i/o f t fsmc_ a 18 , tim4 _ch2 , event o ut - 83 - 102 v ss s t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
stm32f437xx pinouts and pin description doc id 023139 rev 1 45/82 - 84 j1 3 103 v dd s 6 1 85 m14 104 pd1 4 i/o f t fsmc_d0 , tim4_c h3 , event o ut 6 2 86 l1 4 105 pd1 5 i/o f t fsmc_d1 , tim4_c h4 , event o ut - 8 7 l 1 5 106 pg2 i /o ft fsmc_ a 12 , event o u t - 8 8 k 15 107 pg3 i /o ft fsmc_ a 13 , event o u t - 8 9 k 14 108 pg4 i /o ft fsmc_ a 14 , event o u t - 9 0 k 13 109 pg5 i /o ft fsmc_ a 15 , event o u t - 9 1 j1 5 110 pg6 i /o ft fsmc _in t 2, even t o ut , dc mi_d1 2 - 9 2 j1 4 111 pg7 i /o ft fsmc_ i n t 3, u sar t6_c k, event o ut , d c mi_d13 - 9 3 h14 112 pg8 i /o ft usar t6_r ts , eth_pp s_out , e vent o ut , spi6_nss - 94 g 12 113 v ss s - 95 h 13 114 v dd s 6 3 96 h15 115 pc6 i /o ft i2s2_mck , t i m8 _ch1 , sdio_d6, usar t6_tx , dcmi_d 0 , tim3_ ch1 , event o ut 6 4 97 g15 116 pc7 i /o ft i2s3_mck , t i m8 _ch2 , sdio_d7, usar t6_rx , dcmi_d 1 , tim3_ ch2 , event o ut 6 5 98 g14 117 pc8 i /o ft tim8_ch3 , sdio_ d 0, tim3_ ch3 , u sar t6_ck , dcmi_d2, event o ut 6 6 99 f14 118 pc9 i /o ft i2 s_cki n , mco 2 , tim8_ch4, sdio_ d 1, i2 c3_sd a, d c mi_ d 3, tim3_ch4, event o ut 6 7 10 0 f 15 119 p a 8 i /o ft mco1, usar t1_ck, tim1_ch1, i2c3_ s cl, o t g_fs _so f , e vent o ut 6 8 10 1 e 15 120 p a 9 i /o ft usar t1_tx, tim1_c h2, i2c3 _smba, dcmi_d0 , event o ut ot g _ f s _ v b u s t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
pinouts and pin description stm32f437xx 46/82 doc id 023139 rev 1 6 9 10 2 d 15 121 p a 10 i/o f t usart1_rx, tim1_ch3, otg_fs_id, dcmi_d1, eventout 7 0 10 3 c 15 122 p a 11 i/o f t usar t1_cts , c a n1 _rx, tim1 _ch4 , o t g_ fs_dm, event o ut 7 1 10 4 b 15 123 p a 12 i/o f t usar t1 _r ts , ca n1 _t x, tim1_ e tr , o t g_ fs_dp , event o ut 7 2 10 5 a 15 124 pa 1 3 (jtm s-swdio) i/o f t jtms-swdio , e vent o ut 7 3 10 6 f 13 125 v cap_2 s 7 4 10 7 f 12 126 v ss s 7 5 10 8 g 13 127 v dd s - - e12 128 ph13 i/o f t tim8_c h1n , can1_tx, event o ut - - e13 129 ph14 i/o f t tim8 _ch2n, dcmi_d4 , event o ut - - d13 130 ph15 i/o f t tim8_ch3 n, d c m i_d1 1 , event o ut - - e14 131 pi0 (6 ) i/ o f t tim5_ch4 , spi2 _ nss , i2s2_w s , d c mi_d13, event o ut - - d14 132 pi1 (6 ) i/ o f t spi2_sc k , i2 s2_ck, dcmi_d8, event o ut - - c14 133 pi2 i /o ft tim8_ch4 , spi2_miso , dcm i _d9, i2s2e xt _ sd , event o ut - - c13 134 pi3 i /o ft tim8_etr, spi2_mosi, i 2 s2 _sd , d c mi _d 1 0 , event o ut - - d 9 135 v ss s - - c 9 136 v dd s 7 6 10 9 a 14 137 pa 1 4 (jtck - swclk) i/o f t jtck-swclk, event o ut 7 7 11 0 a 13 138 pa 1 5 (jtdi) i/ o f t jt di, spi3_nss , i2s3_ws , tim2 _ch1_ e tr , sp i1_nss , event o ut t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
stm32f437xx pinouts and pin description doc id 023139 rev 1 47/82 7 8 11 1 b 14 139 pc1 0 i/o f t spi3_sck/i2s3_ck , u a r t 4_ t x , s d i o _ d 2, dcmi_d8 , u sar t3_tx, event o ut 7 9 11 2 b 13 140 pc1 1 i/o f t u a r t 4_rx, spi3_miso , sdio_d 3, d c m i_d4, usar t3_rx , i2s3e xt_sd , event o ut 8 0 11 3 a 12 141 pc1 2 i/o f t u a r t 5_t x , sdio_ck , d c mi_d9, spi3_ m osi, i2s3_sd , usar t3_ck , event o ut 8 1 11 4 b 12 142 pd0 i /o ft fsmc _d2, c a n1_r x, event o ut 8 2 11 5 c12 143 pd1 i /o ft fsmc_d3, can1_ t x , event o ut 8 3 11 6 d12 144 pd2 i /o ft tim3_e tr, u a r t 5_r x, sdio _cmd , d cmi _d1 1 , event o ut 8 4 11 7 d11 145 pd3 i /o ft fsmc_cl k , usar t2_cts , event o ut , s pi2_sck, i2s2_ck , dcm i_d5 8 5 11 8 d10 146 pd4 i /o ft fsm c _no e , u sar t2_r ts , event o ut 8 6 11 9 c11 147 pd5 i /o ft fs mc_nwe , u sar t2_tx, event o ut - 12 0 d 8 148 v ss s - 12 1 c 8 149 v dd s 8 7 12 2 b 11 150 pd6 i /o ft fsmc_nw a it , us ar t2_rx, e vent o ut , spi3_mosi, i2s3 _mosi, d c mi_d10 8 8 12 3 a 11 151 pd7 i /o ft usar t2_ck, fsmc_ne1 , fsmc_nce 2, event o ut - 1 2 4 c10 152 pg9 i /o ft usar t6_rx, fsmc_ne2 , fsmc_nce 3, event o ut - 1 25 b10 153 pg10 i/o f t fsmc_ nce4_1 , fsmc_ne3 , event o ut , dcmi_d2 t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
pinouts and pin description stm32f437xx 48/82 doc id 023139 rev 1 - 1 26 b9 154 pg11 i/o f t fsmc_nce4_2, eth_mii_tx_en, eth _rmii_tx_en, eventout, dcmi_d3 - 1 27 b8 155 pg12 i/o f t f s mc_ne 4 , usar t6_r ts , eve nt out , s p i 6_m i so - 1 28 a8 156 pg13 i/o f t fsmc _a24, u sar t6_c ts , eth_ mii_txd0, eth_rmii_ t xd0, e vent o ut , spi6_sck - 1 29 a7 157 pg14 i/o f t fsmc_a25, usar t6_ t x, eth_mii_txd1, eth_rmii_ t xd1, eve nt out , s p i 6_m o si - 13 0 d 7 158 v ss s - 13 1 c 7 159 v dd s - 1 32 b7 160 pg15 i/o f t usar t6_cts , dcm i_d13 , event o ut 8 9 13 3 a 10 161 pb3 (jtdo/ tra c esw o) i/ o f t jtdo/tra cesw o , spi3_sck/i2s3_ck , t i m 2 _ ch2 , s p i 1_sc k, event o ut 9 0 13 4 a 9 162 pb4 (n jt rs t ) i/ o f t njtrst , spi3_mis o , tim3_ch1, spi1_miso , i2s3e xt _ sd , e v ent out 9 1 13 5 a 6 163 pb5 i/o f t i2 c1_smba, c a n2 _rx, o t g_hs_ulpi_d7, eth_pps_out , tim 3 _ch2, spi1_mosi, spi3_mosi, dcm i _d10 , i2s3_sd , event o ut 9 2 13 6 b 6 164 pb6 i/o f t i2 c1_scl , tim4_c h1 , can 2_tx, dcmi_d5 , usar t1_tx, event o ut 9 3 13 7 b 5 165 pb7 i/o f t i2 c1_sd a , fsmc_n l , dcmi_vsync , usar t1 _rx, tim4 _ch2 , event o ut 9 4 13 8 d 6 166 boo t 0 i b v pp t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
stm32f437xx pinouts and pin description doc id 023139 rev 1 49/82 9 5 13 9 a 5 167 pb8 i/o f t tim4_ch3 , sdio_ d 4, tim10_ ch1, dcmi_d 6 , e t h_mi i_txd3, i2c1_scl, can1_rx, event o ut 9 6 14 0 b 4 168 pb9 i/o f t spi2_nss/i2s2_ws , tim4 _ch4 , tim11_ ch1, sdio_d 5, d c m i_d7, i2c1 _sd a , c a n1 _tx, event o ut 9 7 14 1 a 4 169 pe0 i/o f t tim4_etr, fsmc_nbl0 , dcmi_d2, e vent o ut , ua r t 8 _ r x 9 8 14 2 a 3 170 pe1 i/o f t fsmc _nbl1, dcmi_d3 , event o ut , u a r t 8_tx 99 - d 5 - v ss s - 1 43 c6 1 7 1 pd r_ o n i f t 100 14 4 c 5 172 v dd s - - d 4 173 pi4 i /o ft tim 8 _bkin, d c mi_d5, event o ut - - c 4 174 pi5 i /o ft tim8_ch1, d c mi_vsy nc , event o ut - - c 3 175 pi6 i /o ft tim 8 _ c h 2 , d c mi _d 6, event o ut - - c 2 176 pi7 i /o ft tim 8 _ c h 3 , d c mi _d 7, event o ut 1. fu nction availability depends on the chosen de vice. 2. pc13, pc14, pc15 and pi8 are supplied through the power switch. since th e switch only sinks a limited amou nt o f current (3 ma ), the use of gpios pc13 to pc15 and p i 8 in ou tput mode is limited : - t he speed should not exceed 2 mhz with a maximum load o f 30 pf . - t hese i/os must not b e use d as a cu rrent source (e.g. to drive an led ) . 3. main functio n after th e first ba ckup domain pow er-up . later o n, it de pends on the contents of the r t c registers even afte r re set (because th ese registers are not reset by the main rese t) . fo r d etails on how to mana ge these i/os, refer to the r t c re gister d e scription se cti ons in th e stm32f 4xx re ference manual, avai lable fro m the stmicr oelectronics website : ww w.st. c om. 4. ft = 5 v tolerant e x cept when in an alog mo de or oscilla t or mode (for pc 1 4, pc15, ph0 a nd ph1). 5. if the dev ice i s deli v ere d i n an ufbga176 or lqfp 176 pack a ge and the bypass_reg pi n i s s e t to vdd (regulator off/internal rese t on mode), the n pa0 is used as an in ternal reset (a ctive low). 6. pi0 and pi1 canno t be used in i2s2 full-d uplex mode. t a b l e 7. stm 32f 43x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pi n nu mb er p i n name (function aft e r r eset) (1) pin type i/ o stru ctu r e no te s alternate functions a d d itional f u nct i ons lq fp10 0 lq fp14 4 ufbga 176 lq fp17 6
pinouts and pin description stm32f437xx 50/82 doc id 023139 rev 1 t a b l e 8. f s m c pin def i nition pins (1) fsmc lq fp100 (2 ) cf n o r/psram/ sram nor/psr a m mux nand 16 bit pe 2 a 23 a23 y es pe 3 a 19 a19 y es pe 4 a 20 a20 y es pe 5 a 21 a21 y es pe 6 a 22 a22 y es pf0 a 0 a 0 - pf1 a 1 a 1 - pf2 a 2 a 2 - pf3 a 3 a 3 - pf4 a 4 a 4 - pf5 a 5 a 5 - pf6 n iord - pf7 n reg - pf8 n io wr - pf9 c d - pf10 intr - pf12 a6 a6 - pf13 a7 a7 - pf14 a8 a8 - pf15 a9 a9 - pg0 a 10 a10 - pg1 a 11 - pe 7 d 4 d 4 d a4 d4 y e s pe 8 d 5 d 5 d a5 d5 y e s pe 9 d 6 d 6 d a6 d6 y e s pe10 d 7 d 7 d a7 d7 y e s pe11 d 8 d 8 d a8 d8 y e s pe12 d 9 d 9 d a9 d9 y e s pe13 d 10 d10 d a10 d10 y e s pe14 d 11 d11 d a11 d11 y e s pe15 d 12 d12 d a12 d12 y e s pd8 d 13 d13 d a13 d 13 y e s pd9 d 14 d14 d a14 d 14 y e s
stm32f437xx pinouts and pin description doc id 023139 rev 1 51/82 pd10 d 1 5 d 15 d a 15 d15 y e s pd11 a16 a 16 cle y es pd12 a17 a 17 ale y es pd13 a18 a 18 y e s pd14 d0 d0 d a 0 d0 y e s pd15 d1 d1 d a 1 d1 y e s pg2 a 12 - pg3 a 13 - pg4 a 14 - pg5 a 15 - pg6 i nt2 - pg7 i nt3 - pd0 d 2 d 2 d a2 d2 y e s pd1 d 3 d 3 d a3 d3 y e s pd3 c lk c l k y es pd 4 n oe noe n oe noe y e s pd 5 n we nwe n we nwe y e s pd6 n w ait nw ait n w ait nw ait y es pd 7 n e1 ne1 nce2 y e s pg9 n e2 ne2 nce3 - pg10 nce4_1 ne3 n e3 - pg11 nce4_2 - pg12 ne4 n e4 - pg13 a24 a 24 - pg14 a25 a 25 - pb 7 n ad v n ad v y es pe 0 n bl0 n bl0 y es pe 1 n bl1 n bl1 y es 1. fu ll fsmc fea t ures are a v aila ble on lqf p 144, lqfp176, and uf b g a176. t he features available on smaller p a ckages are g i ven in the dedicated packag e column. 2. ports f and g are not available in dev ices delivere d in 1 00-pin packag e s. t a b l e 8. f s m c pin def i nition (c ont in u e d) pins (1) fsmc lq fp100 (2 ) cf n o r/psram/ sram nor/psr a m mux nand 16 bit
pinouts and pin description stm32f437xx 52/82 doc id 023139 rev 1 t a b l e 9. alte rna t e f unc tion mapp in g po r t af0 a f 1 af 2 a f 3 af 4 a f5 af6 a f7 af 8 a f9 af10 af 1 1 af 1 2 af13 af14 af15 s y s t im1/2 t im3 / 4/5 t im8 / 9/10 /11 i 2c1 / 2/3 s p i 1 /2/4/ 5 /6 i2 s2/i 2s2e x t s p i3 /i2s e xt / i2s 3 us ar t1/2/ 3 / i2s3 e x t u a r t 4/5/7/ 8 us ar t 6 can1/can2 / t i m 1 2/ 1 3 / 14 ot g _ f s / o t g _ h s e t h fs m c / s d i o / ot g _ f s dcmi po r t a pa 0 t i m2_c h1 ti m2 _ e tr ti m 5_ ch1 ti m8_etr usar t 2 _ c t s u a r t 4 _ t x et h_ mi i _ c r s event o ut p a 1 t im2_c h2 t i m5_c h2 usar t2 _r ts u a r t 4_r x et h _ mi i _rx_cl k et h_rmii _ref _clk event o ut p a 2 t i m 2_c h3 ti m5_c h3 ti m9_c h1 u s a r t2_tx eth_mdi o event o ut p a 3 t i m 2_c h4 ti m5_c h4 ti m9_c h2 usar t2_rx o t g_hs_ul p i _ d0 et h _mi i _ col event o ut pa 4 s p i 1_nss spi 3_nss i2s3_w s usar t2_ck o t g_hs_sof dcmi _ hsync event o ut pa 5 t i m2_c h1 ti m2 _ e tr tim8 _ch1n s p i 1_sck o t g _ h s _ulpi _ ck event o ut p a 6 t i m 1_bki n ti m3_c h1 t i m8_bki n spi 1_mi s o ti m13_ ch1 d c mi _pi x c k event o ut p a 7 t im1 _ ch1n t i m3_c h2 tim8 _ch1n spi1_mo s i t i m14_ ch1 et h _ mi i _ r x_d v e t h_r m ii _ crs_d v event o ut p a 8 m co 1 t im1_c h1 i2c 3_scl usar t 1_ck o t g _ fs_so f event o ut p a 9 t im1_c h2 i2c3 _smba u sa r t 1_t x dcmi _ d0 event o ut p a 10 t i m1_c h3 usar t1_rx o t g _ f s _i d dcmi _ d1 event o ut p a 11 t i m1_c h4 usar t1_ c ts c a n1_rx o t g _fs_d m event o ut p a 12 t i m1_et r usar t1 _r ts can1_t x o tg _f s_dp event o ut pa 1 3 j t m s - s w d i o event o ut p a 14 jtck- s w c lk event o ut pa 1 5 j t d i t i m 2_ ch1 ti m 2 _ e t r s p i 1_nss s p i 3_nss/ i 2 ss3_w s event o ut
stm32f437xx pinouts and pin description doc id 023139 rev 1 53/82 po r t b pb0 tim1 _ch2n t i m3_c h3 tim8 _ch2n o t g_hs_ul p i _ d1 e t h _ m i i _ r x d 2 event o ut pb1 tim1 _ch3n t i m3_c h4 tim8 _ch3n o t g_hs_ul p i _ d2 e t h _ m i i _ r x d 3 event o ut pb2 event o ut pb3 jt d o / tra c e sw o t i m2_c h2 s p i 1_sck spi 3_sck i2s3_ck event o ut pb4 njtrst ti m3_c h1 spi 1_m iso spi3_miso i 2s3e xt_sd event o ut pb5 t i m3_c h2 i2c1 _smba spi1_mo s i spi 3_mosi i2s3_sd c a n2_rx o t g_hs_ul p i _ d7 eth _ p p s _ o ut dcmi _ d10 event o ut pb6 ti m4_c h1 i 2 c 1_scl i 2 s2_ws u sa r t 1_tx can2_tx dcmi _ d5 event o ut pb7 t i m4_c h2 i2 c1_sd a usar t 1_rx fsmc_nl dcmi _ vsync event o ut pb8 t i m4_c h3 t i m10_c h1 i2c 1_scl c a n1_rx et h _mi i _t xd3 sd i o _ d 4 dcmi _ d6 event o ut pb9 t i m4_c h4 t i m11_c h1 i2 c1_sd a s p i 2_nss i2s2_w s can1_tx sd i o _ d 5 dcmi _ d7 event o ut pb10 t im2_c h3 i2c 2_scl s p i 2_sck i 2 s2_ck u s a r t3_tx o t g_hs_ul p i _ d3 eth_ mi i _ rx_er event o ut pb11 t im2_c h4 i2 c2_sd a usar t 3_rx o t g _ hs_ul p i_d4 e t h _ m ii_t x _e n eth _rmii _ tx_en event o ut pb12 t i m 1_bki n i 2 c2 _smba s p i 2_nss i2s2_w s usar t 3_ck c a n2_rx o t g _ hs_ul p i_d5 eth _mii _txd0 et h _r mii_t x d0 o t g_hs_i d event o ut pb13 t i m 1 _ ch1n s p i 2_sck i 2 s2_ck usar t3_ c ts can2_t x o t g _ hs_ul p i_d6 eth _mii _txd1 et h _r mii_t x d1 event o ut pb14 t i m 1 _ ch2n t i m8 _ch2n spi 2_mi s o i 2s2e xt _sd u sar t 3 _r t s ti m12_ ch1 o t g_hs_dm event o ut p b 1 5 r tc_re f i n tim 1 _ch3n tim 8 _ch3n spi 2_mosi i 2 s2_sd ti m12_ ch2 o t g _ h s _dp event o ut po r t c pc0 o t g _ h s _ulpi _ stp event o ut pc1 e t h_md c event o ut pc2 spi 2_mi s o i 2s2e xt _sd o t g _hs_ ulpi _d i r et h _mi i _t xd2 event o ut pc3 spi 2_mosi i 2 s2_sd o t g_hs_ u lpi _ n x t eth _mi i _tx_clk event o ut pc4 eth_ mii_rxd 0 et h _ rmi i _rxd0 event o ut pc5 e t h _m i i _ rx d1 eth _rmi i_rxd1 event o ut pc6 t i m 3_c h1 ti m8_c h1 i 2 s2_mck usar t 6 _t x sd i o _ d 6 dcmi _ d0 event o ut pc7 t i m 3_c h2 ti m8_c h2 i 2 s3_mck usar t 6_r x sd i o _ d 7 dcmi _ d1 event o ut pc8 t im3_c h3 t i m8_c h3 usar t 6_c k sd i o _ d 0 dcmi _ d2 event o ut pc9 m co 2 t im3_c h4 t i m8_c h4 i2 c3_sd a i2s_cki n sd i o _ d 1 dcmi _ d3 event o ut pc10 s p i 3_sck/ i2s 3 s _ ck u s ar t3_tx/ u a r t 4 _ t x sd i o _ d 2 dcmi _ d8 event o ut pc11 / i 2s3e xt _sd spi 3_mi s o u sar t3_rx u a r t 4_r x sd i o _ d 3 dcmi _ d4 event o ut pc12 spi 3_mosi i2s3_sd usar t3_ck u a r t 5 _ t x sdi o _c k dcmi _ d9 event o ut pc13 pc14 pc15 t a b l e 9. alte rna t e f unc tion mapp in g ( c o n tin u ed ) po r t af0 a f 1 af 2 a f 3 af 4 a f5 af6 a f7 af 8 a f9 af10 af 1 1 af 1 2 af13 a f 14 af 15 s y s t im1/2 t im3 / 4/5 t im8 / 9/10 /11 i 2c1 / 2/3 s p i 1 /2/4/ 5 /6 i2 s2/i 2s2e x t s p i3 /i2s e xt / i2s 3 us ar t1/2/ 3 / i2s3 e x t u a r t 4/5/7/ 8 us ar t 6 can1/can2 / t i m 1 2/ 1 3 / 14 ot g _ f s / o t g _ h s e t h fs m c / s d i o / ot g _ f s dcmi
pinouts and pin description stm32f437xx 54/82 doc id 023139 rev 1 po r t d pd0 c a n1_rx fsmc_d2 event o ut pd1 can1_tx fsmc_d3 event o ut pd2 t im3_et r u a r t 5_r x sdi o _cmd dcmi _ d11 event o ut pd3 spi 2_s c k i2s 2_ck us a r t2_ c ts f s mc_c lk dcmi _ d5 event o ut pd4 us a r t2 _r ts f s mc _noe event o ut pd5 u s a r t 2_t x fsmc_nwe event o ut pd6 sp i3_m o s i i2 s 3 _m o s i usar t2_rx f s mc _nw a i t dcmi _ d10 event o ut pd7 usar t2_ck fs m c _n e 1 / f s mc _nce2 event o ut pd8 u s a r t 3_t x fs mc _d13 event o ut pd9 usar t3_rx fs mc _d14 event o ut pd10 usar t3_ck fs mc _d15 event o ut pd11 us a r t3_ c ts fsmc_a16 event o ut pd12 t i m4_c h1 us a r t3 _r ts fsmc_a17 event o ut pd13 t i m4_c h2 fsmc_a18 event o ut pd14 t i m4_c h3 fsmc_d0 event o ut pd15 t i m4_c h4 fsmc_d1 event o ut po r t e pe0 ti m4 _ e tr ua r t 8 _ r x f s mc_n bl0 dcmi _ d2 event o ut pe1 u a r t 8_tx f s mc_bln 1 dcmi _ d3 event o ut pe2 t r a c ec lk spi 4_s c k et h _mi i _t xd3 fsmc_a23 event o ut pe3 tra c ed0 fsmc_a19 event o ut pe4 tra c ed1 spi 4_n s s fsmc_a20 dcmi _ d4 event o ut pe5 tra c ed2 ti m9_c h1 sp i4_m iso fsmc_a21 dcmi _ d6 event o ut pe6 tra c ed3 ti m9_c h2 sp i4_m o s i fsmc_a22 dcmi _ d7 event o ut pe7 ti m1 _ e tr ua r t 7 _ r x fsmc_d4 event o ut pe8 t i m1 _ch1n u a r t 7_tx fsmc_d5 event o ut pe9 ti m1_c h1 fsmc_d6 event o ut pe10 t i m 1 _ ch2n fsmc_d7 event o ut pe11 t i m 1_c h2 spi 4_n s s fsmc_d8 event o ut pe12 t i m 1 _ ch3n spi 4_s c k fsmc_d9 event o ut pe13 t i m 1_c h3 sp i4_m iso fs mc _d10 event o ut pe14 t i m 1_c h4 sp i4_m o s i fs mc _d11 event o ut pe15 t i m 1_bki n fs mc _d12 event o ut t a b l e 9. alte rna t e f unc tion mapp in g ( c o n tin u ed ) po r t af0 a f 1 af 2 a f 3 af 4 a f5 af6 a f7 af 8 a f9 af10 af 1 1 af 1 2 af13 a f 14 af 15 s y s t im1/2 t im3 / 4/5 t im8 / 9/10 /11 i 2c1 / 2/3 s p i 1 /2/4/ 5 /6 i2 s2/i 2s2e x t s p i3 /i2s e xt / i2s 3 us ar t1/2/ 3 / i2s3 e x t u a r t 4/5/7/ 8 us ar t 6 can1/can2 / t i m 1 2/ 1 3 / 14 ot g _ f s / o t g _ h s e t h fs m c / s d i o / ot g _ f s dcmi
stm32f437xx pinouts and pin description doc id 023139 rev 1 55/82 po r t f pf0 i2 c2_sd a fsmc_a0 event o ut pf1 i2c 2_scl fsmc_a1 event o ut pf2 i2c2 _s m b a fsmc_a2 event o ut pf3 fsmc_a3 event o ut pf4 fsmc_a4 event o ut pf5 fsmc_a5 event o ut pf 6 t im10_c h1 spi 5_n s s u a r t 7 _ r x f s mc _ni o rd event o ut pf 7 t im11_c h1 spi 5_s ck u a r t 7_t x fsmc_nr e g event o ut pf8 sp i5_m iso ti m13_ ch1 fsmc_n i o wr event o ut pf9 sp i5_m o s i ti m14_ ch1 f s mc_c d event o ut pf 1 0 fsmc_i n t r dcmi _ d11 event o ut pf 1 1 sp i5_m o s i dcmi _ d12 event o ut pf 1 2 fsmc_a6 event o ut pf 1 3 fsmc_a7 event o ut pf 1 4 fsmc_a8 event o ut pf 1 5 fsmc_a9 event o ut po r t g pg0 fsmc_a10 event o ut pg1 fsmc_a11 event o ut pg2 fsmc_a12 event o ut pg3 fsmc_a13 event o ut pg4 fsmc_a14 event o ut pg5 fsmc_a15 event o ut pg6 f s mc_ i nt2 dcmi _ d12 event o ut pg7 usar t 6_c k f s mc_ i nt3 dcmi _ d13 event o ut pg8 sp i6_ n ss usar t 6_r ts eth _ p p s _ o ut event o ut pg9 usar t 6_r x fs m c _n e 2 / f s mc _nce3 event o ut pg10 fsmc_ nce4_1 / fs m c _n e 3 dcmi _ d2 event o ut pg11 e t h _ m ii_t x _e n eth _rmii _ tx_en f s mc _nce4_2 dcmi _ d3 event o ut pg12 sp i6 _mis o usar t 6_r ts f s mc_n e4 event o ut pg13 sp i6_ s ck ua rt 6 _ c t s eth _mii _txd0 et h _r mii_t x d0 fsmc_a24 event o ut pg14 sp i6 _mo s i usar t 6 _t x eth _mii _txd1 et h _r mii_t x d1 fsmc_a25 event o ut pg15 u s a r t 6_ct s dcmi _ d13 event o ut t a b l e 9. alte rna t e f unc tion mapp in g ( c o n tin u ed ) po r t af0 a f 1 af 2 a f 3 af 4 a f5 af6 a f7 af 8 a f9 af10 af 1 1 af 1 2 af13 a f 14 af 15 s y s t im1/2 t im3 / 4/5 t im8 / 9/10 /11 i 2c1 / 2/3 s p i 1 /2/4/ 5 /6 i2 s2/i 2s2e x t s p i3 /i2s e xt / i2s 3 us ar t1/2/ 3 / i2s3 e x t u a r t 4/5/7/ 8 us ar t 6 can1/can2 / t i m 1 2/ 1 3 / 14 ot g _ f s / o t g _ h s e t h fs m c / s d i o / ot g _ f s dcmi
pinouts and pin description stm32f437xx 56/82 doc id 023139 rev 1 po r t h ph0 ph1 ph2 et h _mi i _ c r s event o ut ph3 et h _mi i _ col event o ut ph4 i2c 2_scl o t g_hs_ u lpi _ n x t event o ut ph5 i2 c2_sd a sp i5_ n ss event o ut ph6 i2c2 _s m b a sp i5_ s ck ti m12_ ch1 e t h _ m i i _ r x d 2 dcmi _ d8 event o ut ph7 i2c 3_scl sp i5 _mis o e t h _ m i i _ r x d 3 dcmi _ d9 event o ut ph8 i2 c3_sd a dcmi _ hsync event o ut ph9 i2c3 _s m b a ti m12_ ch2 dcmi _ d0 event o ut ph10 t i m5_c h1 dcmi _ d1 event o ut ph11 t i m5_c h2 dcmi _ d2 event o ut ph12 t i m5_c h3 dcmi _ d3 event o ut ph13 tim8 _ch1n can1_t x event o ut ph14 tim8 _ch2n dcmi _ d4 event o ut ph15 tim8_ch3n dcmi_d11 eventout po r t i pi0 t im5_c h4 s p i 2_nss i2s2_w s dcmi _ d13 event o ut pi 1 s p i 2_sck i 2 s2_ck dcmi _ d8 event o ut pi2 t im8_c h4 spi2_miso i 2s2e xt_sd dcmi _ d9 event o ut pi3 t im8_et r spi 2_mosi i 2 s2_sd dcmi _ d10 event o ut pi 4 t i m 8_bki n dcmi _ d5 event o ut pi5 t im8_c h1 dcmi _ vsync event o ut pi6 t im8_c h2 dcmi _ d6 event o ut pi7 t im8_c h3 dcmi _ d7 event o ut pi 8 pi 9 c a n1_rx event o ut pi 10 eth _mi i _rx_er event o ut pi 11 o t g_hs_ u lpi _ d i r event o ut t a b l e 9. alte rna t e f unc tion mapp in g ( c o n tin u ed ) po r t af0 a f 1 af 2 a f 3 af 4 a f5 af6 a f7 af 8 a f9 af10 af 1 1 af 1 2 af13 a f 14 af 15 s y s t im1/2 t im3 / 4/5 t im8 / 9/10 /11 i 2c1 / 2/3 s p i 1 /2/4/ 5 /6 i2 s2/i 2s2e x t s p i3 /i2s e xt / i2s 3 us ar t1/2/ 3 / i2s3 e x t u a r t 4/5/7/ 8 us ar t 6 can1/can2 / t i m 1 2/ 1 3 / 14 ot g _ f s / o t g _ h s e t h fs m c / s d i o / ot g _ f s dcmi
stm32f437xx memory mapping doc id 023139 rev 1 57/82 5 memor y mapping th e me mor y ma p is sho w n in fig u r e 12 . figu re 12 . m e m or y m a p 512-mbyte block 7 cortex-m4's internal peripherals 512-mbyte block 6 not used 512-mbyte block 5 fsmc registers 512-mbyte block 4 fsmc bank 3 & bank4 512-mbyte block 3 fsmc bank1 & bank2 512-mbyte block 2 peripherals 512-mbyte block 1 sram 0x0000 0000 0x1fff ffff 0x2000 0000 0x3fff ffff 0x4000 0000 0x5fff ffff 0x6000 0000 0x7fff ffff 0x8000 0000 0x9fff ffff 0xa000 0000 0xbfff ffff 0xc000 0000 0xdfff ffff 0xe000 0000 0xffff ffff 512-mbyte block 0 code sram (16 kb aliased by bit-banding) reserved 0x2000 0000 - 0x2001 bfff 0x2001 c000 - 0x2001 ffff 0x2003 0000 - 0x3fff ffff 0x4000 0000 reserved 0x4000 7fff 0x4000 8000 - 0x4000 ffff 0x4001 0000 reserved 0x5006 0c00 - 0x5fff ffff ahb3 0x6000 0000 - 0xa000 0fff 0xa000 1000 - 0xdfff ffff ms30415v1 ahb2 sram (112 kb aliased by bit-banding) reserved 0x5006 0bff 0x5000 0000 sram (64 kb aliased by bit-banding) 0x2002 0000 - 0x2002 ffff apb1 apb2 0x4001 57ff 0x4001 5800 - 0x4001 ffff reserved 0x4008 0000 - 0x4fff ffff 0x4007 ffff ahb1 reserved flash memory 0x0820 0000 - 0x0fff ffff 0x1fff 0000 - 0x1fff 7a0f 0x1fff c000 - 0x1fff c007 0x0800 0000 - 0x081f ffff 0x0020 0000 - 0x07ff ffff 0x0000 0000 - 0x001f ffff system memory reserved reserved aliased to flash, system memory or sram depending on the boot pins option bytes reserved 0x1fff c008 - 0x1fff ffff 0x1fff 7a10 - 0x1fff 7fff reserved ccm data ram (64 kb data sram) 0x1000 0000 - 0x1000 ffff reserved 0x1001 0000 - 0x1ffe bfff 0x1ffe c000 - 0x1ffe c007 option bytes reserved 0x1ffe c008 - 0x1ffe ffff 0x4002 0000 cortex-m4 internal peripherals 0xe000 0000 - 0xe00f ffff reserved 0xe010 0000 - 0xffff ffff
memory mapping stm32f437xx 58/82 doc id 023139 rev 1 t a b l e 10 . s tm 32f 43x r e gist er bo unda r y a d d r es ses b u s b ou nd a r y a d d r es s p er ip he r a l 0xe00f ffff - 0xffff ffff reser v ed cortex-m4 0xe000 0000 - 0xe00f ffff cortex-m4 internal peripherals 0xa000 1000 - 0xdfff ffff reser v ed ahb3 0xa00 0 0 000 - 0xa000 0 f ff fsmc co ntrol register 0x90 00 00 00 - 0 x 9 f ff ffff fsmc bank 4 0x80 00 00 00 - 0 x 8 f ff ffff fsmc bank 3 0x7 000 00 00 - 0x7 f ff ffff fsmc bank 2 0x60 00 00 00 - 0 x 6 f ff ffff fsmc bank 1 0x5006 0c00- 0x5fff ffff reserved ahb2 0x50 06 080 0 - 0x5 006 0bff rng 0x5 006 04 00 - 0 x 5006 0 7 ff hash 0x5 006 00 00 - 0 x 5006 0 3 ff cr yp 0x5005 0400 - 0x5005 ffff reser v ed 0x5005 0000 - 0x5005 03ff dcmi 0x5004 0000- 0x5004 ffff reser v ed 0x5000 0000 - 0x5003 ffff usb otg fs 0x4008 0000- 0x4fff ffff reserved
stm32f437xx memory mapping doc id 023139 rev 1 59/82 ahb1 0 x 4004 0 000 - 0x400 7 ffff usb o t g h s 0x4002 9400 - 0x4003 ffff reser v ed 0x400 2 9000 - 0x40 02 93ff ethernet mac 0x4 002 8c0 0 - 0 x 4 002 8fff 0 x 4 002 8 800 - 0x400 2 8bff 0x400 2 8400 - 0x40 02 87ff 0x400 2 8000 - 0x40 02 83ff 0x4002 6800 - 0x4002 7fff reser v ed 0x400 2 6400 - 0x40 02 67ff d ma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 5fff reser v ed 0x4002 4000 - 0x 4002 4fff b kpsram 0x4 002 3c0 0 - 0 x 4 002 3fff fla s h i n terf ace reg i ste r 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reser v ed 0x4002 3000 - 0x4002 33ff crc 0x4002 2400 - 0x4002 2fff reser v ed 0x400 2 2000 - 0x40 02 23ff g pioi 0x4 002 1c0 0 - 0 x 4 002 1fff gpioh 0 x 4 002 1 800 - 0x400 2 1bff gpiog 0x400 2 1400 - 0x40 02 17ff g piof 0x400 2 1000 - 0x40 02 13ff g pioe 0x400 2 0c00 - 0x400 2 0fff gpiod 0 x 4 002 0 800 - 0x400 2 0bff gpioc 0x400 2 0400 - 0x40 02 07ff g piob 0x4002 0000 - 0x4002 03ff gpioa 0x4001 5800- 0x4001 ffff reserved t a b l e 10 . s tm 32f 43x r e gist er bo unda r y a d d r es ses ( c o n tin u e d ) b u s b ou nd a r y a d d r es s p er ip he r a l
memory mapping stm32f437xx 60/82 doc id 023139 rev 1 apb2 0x400 1 5400 - 0x40 01 57ff s pi6 0x4001 5000 - 0x4001 53ff spi5 0x4001 4c00 - 0x4001 4fff reser v ed 0 x 4 001 4 800 - 0x400 1 4bff tim11 0x400 1 4400 - 0x40 01 47ff t im10 0x400 1 4000 - 0x40 01 43ff t im9 0x4 001 3c0 0 - 0 x 4 001 3fff exti 0 x 4 001 3 800 - 0x400 1 3bff syscfg 0x400 1 3400 - 0x40 01 37ff s pi4 0x400 1 3000 - 0x40 01 33ff s pi1 0x4001 2c00 - 0x4001 2fff sdio 0x4001 2400 - 0x4001 2bff reser v ed 0x4001 2000 - 0x4001 23ff adc1 - adc2 - adc3 0x4001 1800 - 0x4001 1fff reser v ed 0x400 1 1400 - 0x40 01 17ff u sar t6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0800 - 0x4001 0fff reser v ed 0x400 1 0400 - 0x40 01 07ff t im8 0x4001 0000 - 0x4001 03ff tim1 0x4000 7800- 0x4000 ffff reserved t a b l e 10 . s tm 32f 43x r e gist er bo unda r y a d d r es ses ( c o n tin u e d ) b u s b ou nd a r y a d d r es s p er ip he r a l
stm32f437xx memory mapping doc id 023139 rev 1 61/82 apb1 0x4 000 7c0 0 - 0 x 4 000 7fff u a r t 8 0 x 4 000 7 800 - 0x400 0 7bff u a r t 7 0x400 0 7400 - 0x40 00 77ff d a c 0x400 0 7000 - 0x40 00 73ff p w r 0x4000 6c00 - 0x4000 6fff reser v ed 0 x 4 000 6 800 - 0x400 0 6bff can2 0x4000 6400 - 0x4000 67ff can1 0x4000 6000 - 0x4000 63ff reser v ed 0x4 000 5c0 0 - 0 x 4 000 5fff i2c 3 0 x 4 000 5 800 - 0x400 0 5bff i2c 2 0x400 0 5400 - 0x40 00 57ff i 2c 1 0x400 0 5000 - 0x40 00 53ff u ar t5 0x4 000 4c0 0 - 0 x 4 000 4fff u a r t 4 0 x 4 000 4 800 - 0x400 0 4bff usar t3 0x400 0 4400 - 0x40 00 47ff u sar t2 0x400 0 4000 - 0x40 00 43ff i 2s3 e xt 0x4 000 3c0 0 - 0 x 4 000 3fff spi3 / i2s3 0 x 4 000 3 800 - 0x400 0 3bff spi2 / i2s2 0x400 0 3400 - 0x40 00 37ff i 2s2 e xt 0x400 0 3000 - 0x40 00 33ff i w dg 0x4 000 2c0 0 - 0 x 4 000 2fff wwd g 0 x 4 000 2 800 - 0x400 0 2bff r t c & bkp r egisters 0x4000 2400 - 0x4000 27ff reser v ed 0x400 0 2000 - 0x40 00 23ff t im14 0x4 000 1c0 0 - 0 x 4 000 1fff tim13 0 x 4 000 1 800 - 0x400 0 1bff tim12 0x400 0 1400 - 0x40 00 17ff t im7 0x400 0 1000 - 0x40 00 13ff t im6 0x4 000 0c0 0 - 0 x 4 000 0fff tim5 0 x 4 000 0 800 - 0x400 0 0bff tim4 0x400 0 0400 - 0x40 00 07ff t im3 0x400 0 0000 - 0x4000 03ff tim2 t a b l e 10 . s tm 32f 43x r e gist er bo unda r y a d d r es ses ( c o n tin u e d ) b u s b ou nd a r y a d d r es s p er ip he r a l
package characteristics stm32f437xx 62/82 doc id 023139 rev 1 6 p a c k a g e c h ar acter i st ics 6. 1 p a c k a g e mec h anical data i n or de r t o mee t en viro nme n t a l re qu ire m en ts , st of f e rs th ese de vices in dif f er ent g r ad es of ecop a c k ? pa c k age s , d epe nd ing on th eir le v e l of e n vir onm ent a l com p lian c e . eco p a c k ? spe c if icat ion s , g r ade d e f i nit i on s an d pr od uct sta t us a r e a v aila b l e a t : ww w . st.com . ecop a c k ? is an st tr ade mar k . figu re 13 . l qfp10 0 , 14 x 14 m m 10 0- pin lo w- pr ofile qua d flat p a c k a g e out line 1. drawin g is not to scale . 1l_me d d1 d3 75 51 50 76 10 0 2 6 12 5 e3 e1 e e b pin 1 iden t i f ica t io n sea ti n g p l a n e gage pla n e c a a2 a1 c cc c 0.2 5 mm 0 . 10 in c h l l1 k c t a b l e 11. lq pf10 0 ? 14 x 1 4 mm 1 00- pi n l o w - pr of il e qu ad fl at pac k a g e mec h ani c a l da ta symbol millimeter s i nc hes (1 ) min t yp ma x m in t y p m ax a 1 .600 0 . 0 630 a1 0.050 0.150 0 . 0 020 0 . 0 059 a2 1.350 1.400 1.450 0 . 0 531 0 . 0 551 0 . 0 571 b 0 .170 0.220 0.270 0 . 0 067 0 . 0 087 0 . 0 106 c 0 .090 0.200 0 . 0 035 0 . 0 079 d 1 5. 80 0 1 6. 00 0 16 . 20 0 0. 62 2 0 0. 62 9 9 0. 63 7 8 d1 13 .8 00 14 .0 00 1 4 .2 00 0 . 5 433 0 . 5 512 0 . 5 591 d3 12 .0 00 0 . 4 724
stm32f437xx package characteristics doc id 023139 rev 1 63/82 figu re 14 . r ec ommend ed f oot print 1. dimensions are exp r essed in millimeters. e 1 5. 80 0 1 6. 00 0 16 . 20 0 0. 62 2 0 0. 62 9 9 0. 63 7 8 e1 13 .8 00 14 .0 00 1 4 .2 00 0 . 5 433 0 . 5 512 0 . 5 591 e3 12 .0 00 0 . 4 724 e 0 .500 0 . 0 197 l 0 .450 0.600 0.750 0 . 0 177 0 . 0 236 0 . 0 295 l1 1.000 0 . 0 394 k 0 3 . 5 7 0 3 . 5 7 ccc 0.080 0 . 0 031 1. values in inches a r e conve r ted from mm and rounded to 4 decimal digits. t a b l e 11. lq pf10 0 ? 14 x 1 4 mm 1 00- pi n l o w - pr of il e qu ad fl at pac k a g e mec h ani c a l da ta symbol millimeter s i nc hes (1 ) min t yp ma x m in t y p m ax 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906
package characteristics stm32f437xx 64/82 doc id 023139 rev 1 figure 1 5 . l q f p1 44 , 2 0 x 2 0 m m , 1 4 4 - p i n lo w - pr of il e qua d fl at pac k a g e out line 1. drawin g is not to scale . d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa 2 a 1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a t a b l e 12. lq fp14 4, 2 0 x 20 mm, 144 -p in l o w-p r of i l e q u ad f l a t pa c k a g e me c h ani c al d a ta symbol mi lli meter s inc h es (1) min t yp max m in t y p m ax a 1 .60 0 0.063 0 a1 0.050 0 . 15 0 0 .0 020 0.005 9 a2 1.350 1.4 0 0 1 .45 0 0 . 0 531 0.05 51 0.057 1 b 0 .170 0.2 2 0 0 .27 0 0 . 0 067 0.00 87 0.010 6 c 0 .090 0 . 20 0 0 .0 035 0.007 9 d 2 1 . 8 0 0 22.00 0 22.200 0 . 8 583 0.86 61 0 . 8 7 4 d1 19 .8 00 20.00 0 20.200 0 . 7 795 0.78 74 0.795 3 d3 17.50 0 0 .689 e 2 1 . 8 0 0 22.00 0 22.200 0 . 8 583 0.86 61 0.874 0 e1 19 .8 00 20.00 0 20.200 0 . 7 795 0.78 74 0.795 3 e3 17.50 0 0 .68 9 0 e 0.5 00 0.01 97 l 0 .450 0.6 0 0 0 .75 0 0 . 0 177 0.02 36 0.029 5
stm32f437xx package characteristics doc id 023139 rev 1 65/82 figu re 16 . r ec ommend ed f oot print 1. dimensions are exp r essed in millimeters. l1 1.0 0 0 0 .03 9 4 k 0 3 . 5 7 0 3 . 5 7 ccc 0 . 08 0 0 .0 03 1 1. values in inches a r e conve r ted from mm and rounded to 4 decimal digits. t a b l e 12. lq fp14 4, 2 0 x 20 mm, 144 -p in l o w-p r of i l e q u ad f l a t pa c k a g e me c h ani c al d a ta symbol mi lli meter s inc h es (1) min t yp max m in t y p m ax ai14905c 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 1 36 37 72 73 108 109 144
package characteristics stm32f437xx 66/82 doc id 023139 rev 1 fi gu re 17 . u fbga17 6+25 - ul tra t h i n fi ne pi t c h bal l gr id a rra y 10 10 0. 6 mm, p a c k a g e out line 1. drawin g is not to scale . t a b l e 13 . u fbga17 6+25 - ul tra t hi n fi ne pi t c h bal l gr id a rra y 10 10 0. 6 mm me c h ani c al d a ta symbol mill imeter s i nc hes (1 ) 1. values in inch es are conve r ted from mm and rounded to 4 d e cimal digits. min t yp max m in t y p m ax a 0 .4 60 0.5 30 0 .6 00 0 . 0 181 0.02 09 0.023 6 a1 0 . 0 5 0 0 .0 80 0 . 1 1 0 0 .00 2 0.00 31 0.004 3 a4 0 . 4 0 0 0 .4 50 0 . 5 0 0 0 .0 157 0.01 77 0.019 7 b 0 .2 30 0.2 80 0 .3 30 0 . 0 091 0.01 10 0.013 0 d 9 .900 10.00 0 10.100 0 . 3 898 0.39 37 0.397 6 e 9 .900 10.00 0 10.100 0 . 3 898 0.39 37 0.397 6 e 0.6 50 0.02 56 f 0 .425 0.4 50 0 .4 75 0 . 0 167 0.01 77 0.018 7 ddd 0 . 0 8 0 0 .003 1 eee 0 . 1 5 0 0 .005 9 fff 0 .0 80 0.003 1 seating plane c a2 c ddd a1 a e f f e r a0e7_me_v3 a 15 1 bottom view ball a1 d e ball a1 top view
stm32f437xx package characteristics doc id 023139 rev 1 67/82 figu re 18 . l qfp17 6 24 x 2 4 mm, 17 6-pin lo w- pr ofile qua d f l at pa c k a g e out line 1. drawing is not to scale . ccc c seating plane c aa 2 a1 c 0.25 mm gauge plane hd d a1 l l1 k 89 88 e he 45 44 e 1 176 pin 1 identification b 133 132 1t_me zd ze t a b l e 14. lq fp17 6, 2 4 x 24 mm, 176 -p in l o w-p r of i l e q u ad f l a t pa c k a g e me c h ani c al d a ta symbol mi lli meter s inc h es (1) min t yp max m in t y p m ax a 1 .60 0 0.063 0 a1 0.050 0 . 15 0 0 .0 020 a2 1.350 1 . 45 0 0 .0 531 0.006 0 b 0 .170 0 . 27 0 0 .0 067 0.010 6 c 0 .090 0 . 20 0 0 .0 035 0.007 9 d 2 3 . 9 0 0 24.100 0 . 9 409 0.948 8 e 2 3 . 9 0 0 24.100 0 . 9 409 0.948 8 e 0.5 00 0.01 97 hd 25 .9 00 26.100 1 . 0 200 1.027 6 he 25 .9 00 26.100 1 . 0 200 1.027 6 l 0 .450 0 . 75 0 0 .0 177 0.029 5 l1 1.0 0 0 0 .03 9 4 zd 1 . 25 0 0 .0 49 2 ze 1 . 25 0 0 .0 49 2 ccc 0 . 08 0 0 .0031 k 0 7 0 7 1. values in inches a r e conve r ted from mm and rounded to 4 decimal digits.
package characteristics stm32f437xx 68/82 doc id 023139 rev 1 figu re 19 . l qfp17 6 rec o mmend ed f oot print 1. dimensions are expr essed in millimeters. 1t_fp_v1 133 132 1.2 0.3 0.5 89 88 1.2 44 45 21.8 26.7 1 176 26.7 21.8
stm32f437xx package characteristics doc id 023139 rev 1 69/82 6. 2 thermal c h aracteristi c s th e ma xim u m ch ip-ju n ct ion t e mp er a t u r e , t j max , in deg rees celsius , ma y be calc ulated u s in g th e f o llo wing e qua tio n : t j max = t a max + ( p d ma x x ja ) wh er e: t a ma x is t h e m a xim u m am bien t t e m per a t ure in c, ja is th e pa c k a g e ju nctio n - t o - a m bie n t t h er ma l resist ance , in c/w , p d max is t h e sum of p int m a x and p i/o ma x (p d max = p in t max + p i/o ma x) , p int m a x is th e pr od u ct of i dd an d v dd , e xpressed in w a tts . this is the maxim u m chip int e r nal p o w e r . p i/o ma x r epr esen ts t he ma xim u m po w e r dissipat ion on ou tp ut pins wh er e: p i/o max = (v ol i ol ) + (( v dd ? v oh ) i oh ), t a king i n t o acco un t t he act u a l v ol / i ol an d v oh / i oh o f th e i/ os at lo w an d h i gh le v e l in th e application. ref e renc e document jesd 51 -2 in te g r at ed c i rcu i ts the r m a l t e st m e th od en viro n m e n t c o n d it ion s - n a t u r a l con v ection (still air). a v a ilab l e from ww w . jedec.org. t a b l e 15 . p a c k a g e t h er mal c h ara c te ri st ic s (1) 1. tbd stand s for ?to be defin ed?. symbol p a r a meter v a l ue unit ja the rmal res i sta n ce junction-ambie nt l q fp100 - 14 14 mm/ 0.5 mm pi tch 43 c/w the rmal res i sta n ce junction-ambie nt l q fp144 - 20 20 mm/ 0.5 mm pi tch 40 the rmal res i sta n ce junction-ambie nt l q fp176 - 24 24 mm/ 0.5 mm pi tch 38 the rmal res i sta n ce junction-ambie nt u f bga1 76 - 1 0 10 mm/ 0. 65 mm pitch 39
part numbering stm32f437xx 70/82 doc id 023139 rev 1 7 p a r t n u mbering f o r a list of a v ailab l e op t i ons ( s pee d, p a c k ag e , et c. ) o r f o r fu r t h e r inf o r m at ion o n an y aspe ct of this de vice , please contact y our neares t st sales of fice . t a b l e 16. o r de ri ng in f o rmat i o n sc he me example : stm32 f 4 3 7 v i t 6 xxx de vice fam i l y stm32 = arm-ba sed 32-b i t microcon trol ler pr od uct typ e f = ge neral-pu r po se de vice subfa m il y 437= st m32f 43x, connect i vity , usb o t g f s /hs , camer a interf ace , eth e r net, cr yp tog r aph ic a cce leration pi n co un t v = 100 pins z = 14 4 pins i = 1 76 pin s fl as h memo r y si z e g = 10 24 kb ytes of flash memor y i = 2 048 kb ytes of flash memor y pa c k a g e t = lq fp h = ufbga t e mpe r ature rang e 6 = industr ia l temp er ature range , ?40 to 85 c . 7 = industr ia l temp er ature range , ?40 to 105 c . op tio n s xxx = pr og r a mmed par t s tr = tap e a nd reel
stm32f437xx application block diagrams doc id 023139 rev 1 71/82 appendix a application b l oc k dia g rams a.1 main applications ver s us pac k a g e ta b l e 1 7 giv e s e x a m ple s of co nf igu r at ion s f o r e a ch pa c k a g e . t a b l e 17. ma i n a ppl i cat i ons v e r s us pa c k a g e f o r st m32 f 43 7xx mi cr oc ont r o l l e r s 10 0 pi ns 14 4 pi ns 1 7 6 p i n s con f ig 1 c on fig2 con f ig3 c o n f i g 4 c onf ig 1 c on fig 2 c on fig3 conf ig4 c onf ig1 c o n f i g 2 usb 1 o t g f s xxx - x x x f s xxxxx xxxx usb 2 hs ul pi x - - - x x x x o t g f s x xx xx f s xxxxx xxxx x et he rn et m i i - - xx xxx x r m i i - xxxx xxxx x sp i/i2s2 sp i/i2s3 x (1 ) xxxx xxxx x sdio sdio sdio or dcmi sdio o r dcmi sdio o r dcmi x s d io o r dc mi x sdio o r dcmi xx x dcmi 8 b it s da ta x x x x x 10bi t s data xx x x x 12bi t s data xx x x x 14bi t s data ---- x x x x fsmc nor/ ram mux e d xxxxx xxxx x nor/ ram x xxxx x n a n d xxxxx xxxx x c f ---- x xxxx x can - xxx - - xx - x 1. only spi/i2s3 is a v aila ble.
application block diagrams stm32f437xx 72/82 doc id 023139 rev 1 a.2 application e x ampl e wi th regulator off figu re 20 . r eg ula t o r off/inte rna l re set on 1. th is mode is a v aila ble on ly on uf bga176 and lqfp176 p a ckages. 2. in regulator bypass mo de, pa0 is used as power-on reset. the connection between p a 0 a nd nrst can consequently prevent debug connection . if the debug conn ec tion unde r reset or pre-reset is requi red, the u s er must manage the rese t and th e power-on reset separately. figu re 21 . r eg ula t o r off/inte rna l re set off 1. this mode is available only on ufbga176 and lqfp176 packages. bypass_reg vcap_1 ai18498 vcap_2 pa 0 nrst application reset signal (optional) 1.2 v v dd power-down reset risen after vcap_1/vcap_2 stabilization bypass_reg vcap_1 vcap_2 pa 0 1.2 v v dd power-down reset risen before vcap_1/vcap_2 stabilization nrst vdd vdd application reset signal (optional) v cap_1/2 monitoring ext. reset controller active when v cap_1/2 < 1.08 v pdr_on pdr_on byp ass_reg vcap_1 ai18499 vcap_2 nrst 1.2 v vdd vdd v dd monitoring ext. reset controller active when v dd < 1.65 v or v cap_1 /v cap_2 < 1.08 v vdd pdr_on vdd pa0
stm32f437xx application block diagrams doc id 023139 rev 1 73/82 a.3 usb o t g full speed (f s) interface sol u tions figu re 22 . u sb c ont r o ller co nfigu r ed as periphe ral- onl y a nd use d in full s p ee d mode 1. external vo ltage regulator o n ly needed when build ing a v bus powere d device. 2. th e same application can be developed using th e otg hs in fs mode to a c hieve enhan ced performance thanks to the large r x /t x f ifo and to a dedicated dma con troller . figu re 23 . u sb c ont r o ller co nfigu r ed as host - o n l y an d use d in f u ll spe e d mod e 1. th e current limiter is requ ire d o nly if the application h a s to support a v bus p o wered device. a basic power switch can be used if 5 v are ava i lable on the application board. 2. th e same application can be developed using th e otg hs in fs mode to a c hieve enhan ced performance thanks to the large r x /t x f ifo and to a dedicated dma con troller . stm32f4xx 5v to v dd v o lat g e regu lat o r (1 ) v dd vb u s dp v ss p a12/pb15 p a1 1//pb14 us b s t d - b con n ec tor dm osc_in osc _ ou t ms19000v5 stm 32f4xx v dd vbus dp v ss usb st d- a co nnect o r dm gpio+irq gpio en ov e r cu rr ent 5 v p wr osc_in osc_out ms19001v4 current limiter power switch (1) p a12/pb15 p a1 1//pb14
application block diagrams stm32f437xx 74/82 doc id 023139 rev 1 figu re 24 . u sb c ont r o ller co nfigu r ed in dual mode a nd use d in f u ll sp eed mod e 1. external vo ltage regulator o n ly needed when build ing a v bus powere d device. 2. th e current limiter is requ ire d o nly if the application h a s to support a v bus p o wered device. a basic power switch can be used if 5 v are ava i lable on the application board. 3. th e id pin is re quired in dual role only. 4. th e same application can be developed u s ing th e otg hs in fs mode to a c hieve enhan ced performance thanks to the large r x /t x f i fo and to a dedicated dma con t roller. st m 32f4xx v dd vb u s dp v ss p a9/pb13 p a12/pb15 p a1 1/pb14 us b micro-ab connector dm gpio+irq gp i o en o v e r c u rren t 5 v p w r 5 v to v dd v o l t ag e regu l a t o r (1 ) v dd id (3) p a10/pb12 os c _ i n os c _ ou t ms19002v3 current limiter power switch (2)
stm32f437xx application block diagrams doc id 023139 rev 1 75/82 a.4 usb o t g high speed (hs) interface solutions figu re 25 . u sb c ont r o ller co nfigu red as periphe ral, h o st , or d u al-mod e a nd use d in h i gh s p ee d mode 1. it is po ssib le to u s e mco1 or mc o2 to save a crys t al. it is how ever no t manda to ry to clock the stm32f 43x with a 24 or 26 mhz crystal when using usb hs. t he above figure only shows an example of a possible connection. 2. th e id pin is re quired in dual role only. dp stm32f4xx dm v bu s v ss dm dp id (2) usb usb hs ot g ctrl fs p h y ul pi high speed otg phy ulpi_ c l k ul pi_ d [ 7 :0 ] ul pi_ d ir ul pi_ s t p ul pi_ n xt not co nne cted co nn ec t o r mc o1 or mco2 24 or 26 mhz xt (1) pl l xt1 xi ms19005v2
application block diagrams stm32f437xx 76/82 doc id 023139 rev 1 a.5 complete audio pla y er solutions t w o solutions are off e red, illustr a ted in figu re 2 6 an d figu re 2 7 . fig u r e 26 sho w s st or a ge me dia t o au dio d a c/ am plif ier st re amin g using a sof t w ar e code c. th is solu tio n imple m en ts an au dio cr ysta l t o pr o v ide au dio class i 2 s accur a cy on the mast er cloc k (0 .5 % e r r o r m a xim u m, se e th e ser i a l p e r i p her al int e r f a c e se ct ion in t h e re f e re nce ma n ua l f or det ai ls) . figure 26 . c omplet e au dio p l a y e r s o lution 1 fig u r e 27 sho w s st or a ge me dia t o au dio cod e c/ amp lifie r str e a m ing wit h sof synchr oniza tio n of in pu t/ ou tp ut aud io str eam ing u s in g a ha rd w a r e co de c. figu re 27 . c omplet e au dio p l a y e r s o lution 2 cortex-m4f core up to 168 mhz otg (host mode) + phy spi/ fsmc spi/ sdio gpio i2s xt al 25 mhz or 14.7456 mhz usb mass-storage device mmc/ sdcard lcd touch screen control buttons dac + audio ampli file system program memory audio codec user application stm32f4xx ms19922v2 cortex-m4f core up to 168 mhz otg + phy gpio i2s usb mass-storage device mmc/ sdcard lcd touch screen control buttons audio ampli file system program memory audio codec user application stm32f4xx ms19923v2 sof sof synchronization of input/output audio streaming xtal 25 mhz or 14.7456 mhz spi/ fsmc spi/ sdio
stm32f437xx application block diagrams doc id 023139 rev 1 77/82 figu re 28 . a udio pla y er so lut i on using pll , plli2s, usb and 1 c r ys ta l figu re 29 . a udio pll ( p l l i2s) pr o v id in g a c c u rat e i2s c l oc k otg 48 mhz phy xt al 25 mhz or 14.7456mhz stm32f4xx ms19924v1 i2s <0.04% accuracy) dac + audio ampli mclk out sclk mco1/ mco2 plli2s x n2 pll x n1 osc div by m div by p div by q cortex-m4f core up to 168 mhz div by r mclk in mco1pre mco2pre i2s ctl i2 s_ m c k = 25 6 f sa u d i o 1 1 . 2 896 m h z fo r 4 4 . 1 k h z 1 2 . 2 880 m h z f o r 4 8 . 0 k h z i2 s_ m c k plli2s /m m = 1,2 , 3 ,..,6 4 1 m h z 19 2 t o 4 32 m h z n = 19 2,1 9 4 ,..,43 2 i2 s com_ck ph asec vc o /n /r cl kin ph as e l o c k d e t e c t or r = 2,3 , 4, 5,6 , 7 i2 sd = 2 , 3 ,4 . . 1 2 9 ai16041b
application block diagrams stm32f437xx 78/82 doc id 023139 rev 1 fi gu re 30 . m ast er c l oc k (mck) us ed to d r iv e th e e x te rna l au di o d a c 1. i2s_sck is th e i2s se ria l clo c k to the exter nal au dio d a c (not to be confuse d with i2s_ck). figu re 31 . m ast er c l oc k (mck) not use d to drive t h e e x ter n al audio d a c 1. i2s_sck is the i2s serial clock to the exter nal audio dac (not to be confused with i2s_ck). i2 s_ c k i 2 s cont rol l e r i 2 s_ m c k = 25 6 f sa ud i o = 1 1 . 2 896 m h z f o r f sa ud i o = 44 . 1 k h z = 1 2 . 2 880 m h z f o r f sa ud i o = 4 8 . 0 k h z /(2 x 1 6 ) /8 /i 2s d f saud i o i2 s_ s c k (1) = i 2 s_ m c k / 8 f o r 16 -b it s t e r e o fo r 16 -bi t stereo /(2 x 3 2 ) /4 for 32 -bi t stereo f sa udio 2,3, 4,.., 12 9 = i 2 s_ m c k / 4 f o r 32 -b it s t e re o ai16042 i2s c o m _ c k i2 s controller / ( 2 x 16 ) /i 2s d f sa ud io i2 s_s c k (1) for 16-bit s t er e o / ( 2 x 32 ) for 32-bit s t er e o f sa ud io ai16043
stm32f437xx application block diagrams doc id 023139 rev 1 79/82 a.6 ethernet i n terface sol u ti ons figu re 32 . m ii mode us ing a 25 mhz c r y s t a l 1. f hclk must be greater than 25 mhz. 2. pulse pe r secon d when using ieee 1 588 ptp optional signal. figure 3 3 . r m ii wi th a 5 0 mh z os ci lla tor 1. f hclk must be greater than 25 mhz. mcu ethernet mac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 25 mhz mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er mii_tx_clk mii_tx_en mii_txd[3:0] mii_crs mii_col mdio mdc hclk (1) pps_out (2) xt al 25 mhz stm32 osc tim2 t imestamp comparator t imer input trigger ieee1588 ptp mii = 15 pins mii + mdc = 17 pins ms19968v1 mco1/mco2 mcu ethernet mac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 50 mhz rmii_rxd[1:0] rmii_crx_dv rmii_ref_clk rmii_tx_en rmii_txd[1:0] mdio mdc hclk (1) stm32 osc 50 mhz tim2 t imestamp comparator t imer input trigger ieee1588 ptp rmii = 7 pins rmii + mdc = 9 pins ms19969v1 /2 or /20 synchronous 2.5 or 25 mhz 50 mhz 50 mhz
application block diagrams stm32f437xx 80/82 doc id 023139 rev 1 fi gu re 34 . r mi i w i t h a 25 m h z cryst al and phy w i t h pll 1. f hclk must be greater than 25 mhz. 2. the 25 mhz (phy_clk) must be derived directly from the hse oscillator , before the pll block. mcu ethernet mac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 25 mhz rmii_rxd[1:0] rmii_crx_dv rmii_ref_clk rmii_tx_en rmii_txd[1:0] mdio mdc hclk (1) stm32f tim2 t imestamp comparator t imer input trigger ieee1588 ptp rmii = 7 pins rmii + mdc = 9 pins ms19970v1 /2 or /20 synchronous 2.5 or 25 mhz 50 mhz xt al 25 mhz osc pll ref_clk mco1/mco2
stm32f437xx revision history doc id 023139 rev 1 81/82 8 re vision histor y t a b l e 18 . f ull doc ument re vision hist or y da te re v i s i on cha n g e s 09- no v-20 12 1.0 i ni tia l re lea se .
stm32f437xx 82/82 doc id 023139 rev 1 pl ea se r e ad c a re fu lly : inf or m at i on i n t hi s d ocumen t i s p r o vi ded so l el y i n co nnecti on wi th st pr oducts. s t mi cr oelect roni cs nv an d i t s su bsi d i a r i e s (? s t ?) re ser ve th e ri ght t o ma ke ch anges , co rr ec ti o ns, mo di f i c at i on s o r i m p r o vem ent s , t o t hi s d ocume nt , and t he pr oducts a nd ser vi c es de scr i bed h e r ei n at any t i me, with ou t no tic e. al l st pr odu ct s a r e s o l d pu rs ua nt to s t ? s t e r m s an d co nd it i o n s of sal e . pur c h a s e r s a r e so le l y r e s pon si bl e fo r t h e c hoi c e , se le ct i o n an d us e o f th e s t pr od uc ts an d s e r v i c e s d e s c r i b e d he re in , and st as s u m es no li a b i l i t y wh at so ev er r e l a t i n g t o t h e cho i ce, se le ct i o n o r u se o f t h e s t pr odu ct s a nd s e r v i c e s de sc ri be d he re in . no l i c e nse , e x p r e s s o r i m pl i e d , b y e s t o p pel or ot he rw is e, t o an y i n t e l l e c t u a l pr op er ty ri gh t s i s gr an te d u nde r t h i s doc ume n t . i f an y pa rt of t h i s do cume n t re f e r s t o an y t h i r d pa rt y p r o duc t s or se rv ic es i t sh al l n o t be d e e m ed a li ce ns e gr an t b y st fo r t h e use of su ch t h i r d par ty pr od uc ts or ser vi c es, or an y in t el l e ct ual p r o per t y c ont a i n ed t her e i n or con si dered as a war r ant y c over i n g t he u se i n a ny manner w hat s oev er o f su ch th i r d p a r t y pr od uct s o r se rv i ces or a n y i n t e ll e c t u a l pr op er t y co nt ai ne d t her ei n . unle ss o t her w ise se t for t h in s t ?s t e rms and co nditions o f sa le s t disc laims an y ex pres s or imp l ied warrant y wit h r espe ct to th e use and/or sa le of st p roduct s in cluding withou t limit ation imp l ied warrant ie s of merch antab il it y, fitne ss f or a parti cul ar p urpos e (and t heir e quivale nts under the laws of any j urisdiction), o r inf rin gement o f any pat e nt, copy right or oth e r in tel lect ual pro pert y rig ht. unle ss e xpre ssly app roved in w r it ing by two a u thor iz ed st repr esen tative s, st p roduct s are not recommended , author iz ed or warrant ed f or us e in milita ry, air cra ft, sp ace, l i f e sa ving, or l i f e su staining appl ications, nor in p roduct s or sy ste ms where failure or malf unction may resu lt in per sonal inj ury , deat h, or s eve re prop erty o r environme ntal d amage. st p roduct s whic h are not s pecified as "automo t ive grade " may only b e used in autom otive app l ications a t user?s own risk. res al e of st pr oduct s wi t h pr ovisions d i f f er ent f r o m t he s t at eme nt s and/ or t echni c al feat ur es s et f o rt h i n this d ocume nt s hal l i mme di at el y v o i d an y wa rr an t y g r a n t e d by st fo r th e s t p r o duc t or se rv i c e de scr i b e d h e r e i n a n d sh al l no t cr ea te or e x t e n d i n any man n e r wha t s o e v er, a n y l i ab il ity of st. st a nd t h e s t lo go a r e tr ad ema r k s or re gi st er ed t r ad emar ks of s t i n va ri ou s co un tr i es. in f o r m at i on i n t h i s do cu men t su pe rs ed es a nd r e p l a c e s al l i n fo rma t i o n pr ev io us ly s u p p l i e d . th e st l o g o is a re gi ste r e d tr ad ema r k o f s t m icr o e l e c t r o n i c s . a ll ot he r n a m es a r e th e pr op er ty of th ei r r e s p e c tiv e ow n e r s . ? 2 0 1 2 s t mic r o e l ec tr on ic s - a l l ri gh ts re se rv ed s t mi cr oe le ctr o n i c s gr ou p of co mp an ie s aus t r al i a - b el gi um - b r a zi l - can ada - ch ina - cz ech rep ubl i c - f i nl and - fr ance - ger m any - ho ng k ong - i ndi a - is rael - i t a l y - ja pa n - m a l a y s i a - ma lt a - mo ro cc o - p h i l i p pi ne s - si ng ap or e - sp ai n - s w ed en - swi t zer l a n d - un it ed ki ngd om - u n i t e d st at e s of amer i c a www .s t.co m

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